• 한국정보통신학회논문지
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• 제17권2호
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• pp.355-362
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• 2013

TOF(Time-Of-Flight) 센서에 의해 획득된 정보로부터 3차원 깊이 영상(depth image)을 추출하기 위한 위상 연산기의 하드웨어 구현을 기술한다. 설계된 위상 연산기는 CORDIC(COordinate Rotation DIgital Computer) 알고리듬의 vectoring mode를 이용하여 arctangent 연산을 수행하며, 처리량을 증가시키기 위해 pipelined 구조를 적용하였다. 고정 소수점 MATLAB 모델링과 시뮬레이션을 통해 최적 비트 수와 반복 횟수를 결정하였다. 설계된 위상 연산기는 MATLAB/Simulink와 FPGA 연동을 통해 하드웨어 동작을 검증하였으며, TSMC 0.18-${\mu}m$ CMOS 셀 라이브러리로 합성하여 약 16,000 게이트로 구현되었고, 200MHz@1.8V로 동작하여 9.6 Gbps의 연산 성능을 갖는 것으로 평가되었다.

• 전기학회논문지
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• 제67권11호
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• pp.1447-1454
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• 2018

In this paper, the design of robust DSC-PLL(Delayed Signal Cancellation Phase Locked Loop) is proposed for coping with frequency variation. This method shows significant performance for detection of fundamental positive sequence component voltage when the grid voltage is polluted by grid unbalance and frequency variation. The feedback frequency estimation of DSC-PLL is tracking the drift in the phase by unbalance and frequency variation. The robust DSC PLL is to present the analysis on method and performance under frequency variations. These compensation algorithms can correct for discrepancies of changing the frequency within maximum 193[ms] and improve traditional DSC-PLL. Linear interpolation method is adopted to reduce the discretized errors in the digital implementation of the PLL. For verification of robust characteristic, PLL methods are implemented on FPGA with a discrete fixed point based. The proposed method is validated by both Matlab/Simulink and experimental results based on FPGA(XC7Z030).

• 시스템엔지니어링학술지
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• 제12권2호
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• pp.101-114
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• 2016

A model-based systems engineering (MBSE) approach to implementing hardware-based network cybersecurity controls for APR1400 non-safety data network is presented in this work. The proposed design was developed by implementing packet filtering and deep packet inspection functions to control the unauthorized traffic and malicious contents. Denial-of-Service (DoS) attack was considered as a potential cybersecurity issue that may threaten the data availability and integrity of DCS gateway servers. Logical design architecture was developed to simulate the behavior of functions flow. HDL-based physical architecture was modelled and simulated using Xilinx ISE software to verify the design functionality. For effective modelling process, enhanced function flow block diagrams (EFFBDs) and schematic design based on FPGA technology were together developed and simulated to verify the performance and functional requirements of network security controls. Both logical and physical design architectures verified that hardware-based cybersecurity controls are capable to maintain the data availability and integrity. Further works focus on implementing the schematic design to an FPGA platform to accomplish the design verification and validation processes.

• 대한전자공학회논문지TE
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• 제37권3호
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• pp.37-44
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• 2000

본 논문에서는 실시간 데이터 압축을 위한 Lempel-Ziv 압축기의 효과적인 하드웨어 구조를 제안한다. 일반적으로 Lempel-Ziv 알고리즘의 구현에서는 matching 바이트 탐색과 dictionary 버퍼의 누적된 shift 동작이 처리 속도에 가장 중요한 문제이다. 제안하는 구조에서는 dictionary 크기를 최적화하는 방법과 복수개의 바이트를 동시에 비교하는 matching 바이트 처리 방법, 그리고 회전 FIEO 구조를 이용하여 shift 동작 제어 방법을 이용함으로써 효과적인 Lempel-Ziv 알고리즘의 처리 구조를 제안하였다. 제안된 구조는 상용 DSP를 사용하여 하드웨어적으로 정확하게 동작함을 검증하였으며, VHDL로 기술한 후 회로 합성을 수행하여 상용 FPGA 칩에 구현하였다. 제안된 구조는 시스템 클락 33㎒, 비트율 256Kbps 전용선에서 오류 없이 동작함을 확인하였다.

• 융합신호처리학회논문지
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• 제2권4호
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• pp.71-76
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• 2001

본 논문에서는 5GHz 대역을 사용하는 고속 무선 LAN의 표준안의 IEEE 802.11a-1999 를 위한 디지털 자동 이득 제어기를 제언한다. 송수신간의 동기화를 위한 신호인 training symbol을 이용하여 수신기에 입력되는 신호의 이득을 측정한다. 측정된 이득을 이상적인 이득과 비교하여 갱신할 이득을 구한다. 갱신 이득은 신호를 증폭하는 GCA(Gain Controlled Amplifer)의 입력 전압으로 변환되어 신호의 증폭도를 제어하게 된다. 본 논문에서는 하드웨어 부담을 줄이기 위해 부분 선형 근사방법을 이용하여 갱신 이득을 본 논문에서 제안한 디지털 자동 이득 제어기는 VHDL을 이용하여 설계하였으며, Xilinx cAD tool을 이용하여 timing verification을 수행하였다.

• 한국통신학회논문지
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• 제27권12C호
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• pp.1282-1287
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• 2002

본 논문에서는 가정 내의 전화선을 이용한 홈 네트워크 기술인 10Mbps HomePNA(Home Phoneline Networking Alliance) 20 PHY 회로의 설계 및 그에 대한 검증방법을 보여 준다. HomePNA 2.0 PHY 회로는 MII(Media Independent Interface)와 AFE 인터페이스에 의해 외부와 연결된다. 설계된 10Mbps HomePNA 2.0 PHY의 회로의 전체 구조는 Management block IEEE 802.3 CSMA/CD MAC(Media Access Control) block, 변조 및 복조 block으로 크게 구성된다. 설계된 회로는 프로토타입 FPGA PCB 보드를 이용하여 검증하였다. 또한, Linux 기반의 드라이버 프로그램을 개발하여 HomePNA 프레임 데이터 전송의 기본적인 동작을 확인하였으며, HomePNA 2.0 링크 계층 프로토콜의 RNCF(Rate Negotiation Control Function)에 의하여 전송속도의 변화를 확인하였다.

• Nuclear Engineering and Technology
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• 제48권4호
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• pp.1047-1057
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• 2016

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1567-1570
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• 2002

This paper deals with FPGA(Field Programmable Gate Array) implementation of the AAC(Advanced Audio Coding) decoder. On modern computer culture, according to the high quality data is required in multimedia systems area such as CD, DAT(Digital Audio Tape) and modem. So, the technology of data compression far data transmission is necessity now. MPEG(Moving Picture Experts Group) would be a standard of those technology. MPEG-2 AAC is the availableness and ITU-R advanced coding scheme far high quality audio coding. This MPEG-2 AAC audio standard allows ITU-R 'indistinguishable' quality according to at data rates of 320 Kbit/sec for five full-bandwidth channel audio signals. The compression ratio is around a factor of 1.4 better compared to MPEG Layer-III, it gets the same quality at 70％ of the titrate. In this paper, for a real time processing MPEG2 AAC decoding, it is implemented on FPGA chip. The architecture designed is composed of general DSP(Digital Signal Processor). And the Processor designed is coded using VHDL language. The verification is operated with the simulator of C language programmed and ECAD tool.

• 전기전자학회논문지
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• 제21권3호
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• pp.240-243
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• 2017

차량 내부의 전자 장치가 급증함에 따라 CAN(controller area network)에 데이터 병목 현상이 발생하기 시작했다. 이에 따라 CAN을 개량한 CAN-FD(CAN with flexible data rate) 버스가 개발되었는데, 버스 중재 단계(arbitration phase)에서는 CAN과 동일한 속도로 전송하되 데이터 전송 단계(data phase)에서는 훨씬 빠른 속도로 전송함으로서 호환성과 효율성을 모두 높였다. 본 논문에서는 CAN-FD 규격 1.0과 CAN 규격 2.0A, 2.0B를 모두 만족하는 CAN-FD 제어기를 Verilog HDL를 사용하여 설계하고 FPGA로 구현한 뒤 동작을 검증하였다. 0.18um 공정을 사용하여 합성한 결과는 약 46,300 게이트이다.

• Journal of Platform Technology
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• 제6권4호
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• pp.26-33
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• 2018

In this paper, we propose an image retrieval algorithm for real-time processing and design it as hardware. The proposed method is based on the classification of BoWs(Bag of Words) algorithm and proposes an image search algorithm using bit stream. K-fold cross validation is used for the verification of the algorithm. Data is classified into seven classes, each class has seven images and a total of 49 images are tested. The test has two kinds of accuracy measurement and speed measurement. The accuracy of the image classification was 86.2% for the BoWs algorithm and 83.7% the proposed hardware-accelerated software implementation algorithm, and the BoWs algorithm was 2.5% higher. The image retrieval processing speed of BoWs is 7.89s and our algorithm is 1.55s. Our algorithm is 5.09 times faster than BoWs algorithm. The algorithm is largely divided into software and hardware parts. In the software structure, C-language is used. The Scale Invariant Feature Transform algorithm is used to extract feature points that are invariant to size and rotation from the image. Bit streams are generated from the extracted feature point. In the hardware architecture, the proposed image retrieval algorithm is written in Verilog HDL and designed and verified by FPGA and Design Compiler. The generated bit streams are stored, the clustering step is performed, and a searcher image databases or an input image databases are generated and matched. Using the proposed algorithm, we can improve convenience and satisfaction of the user in terms of speed if we search using database matching method which represents each object.