Journal of the Institute of Electronics Engineers of Korea TE (대한전자공학회논문지TE)

The Institute of Electronics and Information Engineers (대한전자공학회)
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An efficient Hardware Architecture of Lempel-Ziv Compressor for Real Time Data Compression

실시간 데이터 압축을 위한 Lempel-Ziv 압축기의 효과적인 구조의 제안

  • Published : 2000.09.01
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Abstract

In this paper, an efficient hardware architecture of Lempel-Ziv compressor for real time data compression is proposed. The accumulated shift operations in the Lempel-Ziv algorithm are the major problem, because many shift operations are needed to prepare a dictionary buffer and matching symbols. A new efficient architecture for the fast processing of Lempel-Ziv algorithm is presented in this paper. In this architecture, the optimization technique for dictionary size, a new comparing method of multi symbol and a rotational FIFO structure are used to control shift operations easily. For the functional verification, this architecture was modeled by C programming language, and its operation was verified by running on commercial DSP processor. Also, the design of overall architecture in VHDL was synthesized on commercial FPGA chip. The result of critical path analysis shows that this architecture runs well at the input bit rate of 256kbps with 33MHz clock frequency.

본 논문에서는 실시간 데이터 압축을 위한 Lempel-Ziv 압축기의 효과적인 하드웨어 구조를 제안한다. 일반적으로 Lempel-Ziv 알고리즘의 구현에서는 matching 바이트 탐색과 dictionary 버퍼의 누적된 shift 동작이 처리 속도에 가장 중요한 문제이다. 제안하는 구조에서는 dictionary 크기를 최적화하는 방법과 복수개의 바이트를 동시에 비교하는 matching 바이트 처리 방법, 그리고 회전 FIEO 구조를 이용하여 shift 동작 제어 방법을 이용함으로써 효과적인 Lempel-Ziv 알고리즘의 처리 구조를 제안하였다. 제안된 구조는 상용 DSP를 사용하여 하드웨어적으로 정확하게 동작함을 검증하였으며, VHDL로 기술한 후 회로 합성을 수행하여 상용 FPGA 칩에 구현하였다. 제안된 구조는 시스템 클락 33㎒, 비트율 256Kbps 전용선에서 오류 없이 동작함을 확인하였다.

Keywords

References

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