• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.992-995
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• 2011

ALADDIN(Advanced Layer-free DDoS Defense INfrastructure) 시스템은 양방향 10Gbps 트래픽을 처리할 수 있는 안티 DDoS 전용 시스템이다. 로드 밸런서 엔진, 안티 DDoS 분석 엔진, PCI-Express 엔진으로 구성된 세 개의 FPGA 기반 하드웨어 엔진과 소프트웨어 엔진으로 이루어진 시스템은 인라인 모드로 동작하면서 Wire-speed 로 패킷을 처리한다. 시스템은 네트워크 레벨의 DDoS 공격뿐만 아니라 어플리케이션 레벨의 DDoS 공격도 실시간으로 탐지하고 대응한다. 본 논문에서는 ALADDIN 시스템의 설계 및 구현, 테스트 결과에 대해 기술한다.

• International journal of advanced smart convergence
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• v.12 no.4
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• pp.26-34
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• 2023

A high-speed data transmission system is designed for the ground inspection equipment of satellite measurement and control. Based on USB2.0, the system consists of interface chip CY7C68013A, programmable logic processing unit EP4CE30F23C8, analog/digital and digital/analog conversion units. The working principle of data transmission is analyzed, and the system software logic and hardware composition scheme are detailed. The system was utilized to output/capture and store specific data packets. The results show that the high-speed data transmission speed can reach 38MB/s, and the system is effective for satellite test requirements.

• Nuclear Engineering and Technology
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• v.56 no.7
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• pp.2557-2562
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• 2024

A type of integrated multiple-single-channel analyzer (IMSCA) is described. The IMSCA works with an input pulse of 2-20 pC, and it can be directly connected to a scintillation detector, which eliminates the need for a linear amplifier. It consists of 64 input ports, so 1-64 detectors can be set by users according to different requirements. Two energy regions for each input channel can be simultaneously analyzed. Another advantage of the IMSCA is that it integrates with a high-speed pulse signal acquisition card and transmits data to the computer through the network. The maximum pulse through-rate is 1.4 MHz, and linearity can reach 0.1%. This IMSCA has been successfully used in enrichment detecting of nuclear fuel rod.

• ETRI Journal
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• v.27 no.5
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• pp.525-532
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• 2005

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.14 no.2
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• pp.136-144
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• 2014

The existing conventional motion controller does not perform well in the presence of nonlinear properties, uncertain factors, and servo lag phenomena of industrial actuators. Hence, a feasible and effective fuzzy self-tuning proportional integral derivative (PID) and feed-forward control scheme is introduced to overcome these problems. In this design, a fuzzy tuner is used to tune the PID parameters resulting in the rejection of the disturbance, which achieves better performance. Then, both velocity and acceleration feed-forward units are added to considerably reduce the tracking error due to servo lag. To verify the capability and effectiveness of the proposed control scheme, the hardware configuration includes digital signal processing (DSP) which plays the main role, dual-port RAM (DPRAM) to guarantee rapid and reliable communication with the host, field-programmable gate array (FPGA) to handle the task of the address decoder and receive the feed-back encoder signal, and several peripheral logic circuits. The results from the experiments show that the proposed motion controller has a smooth profile, with high tracking precision and real-time performance, which are applicable in various manufacturing fields.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.173-178
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• 1999

The Trellis Coded Modulation(TCM) allows the considerable achievements of coding gains compare with conventional multi-level modulation without compromising bandwidth efficiency. In this paper, we are presented a design of the parallel Viterbi decoder for 16-QAM TCM decoder with large constraint length (K=9), which can be applicable for the Digital Audio Broadcasting(DAB) receiver. As a mid-term result, a parallel Branch Metric Calculator (BMC)can compute 16 BMs within 3 clocks and a parallel 16 Add-Compare-Selects (ACS) unit can compute in a single clock. And also, two 256 Path Metric Memories (PMM) 32 Trace Back(TB) memories are specially designed with shuffle exchange switches for 16 parallel accesses. As a VHDL simulation, we can find the correctness of proposed model, which can be operated 16 S per symbol. Now, we are performing the hardware reduction for realtime operation and FPGA implementation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.505-513
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• 2017

As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGA-proven full-custom ASNoC.

• Journal of IKEEE
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• v.24 no.2
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• pp.497-501
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• 2020

Dehaze is essential for autonomous driving and intelligent CCTV to operate normally even in foggy weather. The method of airlight estimation is particularly important in dehaze technology. In this paper, we propose a patch-based airlight estimation algorithm and hardware structure that can reduce the amount of unnecessary computation and effectively estimate the airlight in various input images. Proposed algorithm is compared with the popular quad-tree method, and the hardware design is implemented by using XILINX's xc7z045-ffg900 target board as a structure that can satisfy to international standard 4K video in real time.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.36-43
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• 1999

A new design of a Direct Digital Frequency Synthesizer(DDFS) is presented, where a pipelined Coordinate Rotate Digital Computer(CORDIC) circuit is employed to calculate amplitude values of all the phase angles of sinusoidal waveforms produced. a near-optimal number of pipeline stages is determined based on an error analysis of calculated amplitude values in terms of the number of bits. The DDFS was implemented using a field programmable gate array, yielding a stable operating frequency of 11.75MHz. The measurement results show higher resolution, faster operating speed and simpler fabrication process, compared to ROM-based counterparts. The CORDIC-based DDFS yields 5 times higher resolution than conventional ROM-based versions.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.289-291
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• 2007

The Digital Multimedia Broadcasting(DMB) system is developed to offer high quality audio-visual multimedia contents to the uses by the various portable terminals in the mobile environment. Integrated complex reception platform is required to receive multimedia broadcasting services transmitted from various transmission media. In this paper, we present the design and implementation technic for providing the both of terrestrial and satellite DMB services simultaneously using the same hardware platform. The implemented complex receiving terminal to accommodate these DMB services simultaneously need composed of it RF module. it baseband module, it complex control module and the complex de-multiplexer module. The complex control module is designed using uClinux operating system. The complex de-multiplexer, which perform the functions of the address decoder and each DMB stream de-multiplexer, is implemented. with FPGA device. The implemented platform is tested in a real environment and its performance is satisfied with required performance criteria.