• Journal of Software Assessment and Valuation
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• v.17 no.2
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• pp.161-172
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• 2021

Neuromorphic architecture is drawing attention as a next-generation computing that supports artificial intelligence technology with low energy. However, FPGA embedded boards based on Neuromorphic architecturehave limited resources due to size and power. In this paper, we compared and evaluated the image reduction method using the interpolation method that rescales the size without considering the feature points and the DCT (Discrete Cosine Transform) method that preserves the feature points as much as possible based on energy. The scaled images were compared and analyzed for accuracy through CNN (Convolutional Neural Networks) in a PC environment and in the Nengo framework of an FPGA embedded board.. As a result of the experiment, DCT based classification showed about 1.9% higher performance than that of interpolation representation in both CNN and FPGA nengo environments. Based on the experimental results, when the DCT method is used in a limited resource environment such as an embedded board, a lot of resources are allocated to the expression of neurons used for classification, and the recognition rate is expected to increase.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.381-382
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• 2006

In this paper, we present an efficient architecture for connected speech recognition that can be efficiently implemented with FPGA. The architecture consists of newly derived two-level dynamic programming (TLDP) that use only bit addition and shift operations. The advantages of this architecture are the spatial efficiency to accommodate more words with limited space and the computational speed from avoiding propagation delays in multiplications. The architecture is highly regular, consisting of identical and simple processing elements with only nearest-neighbor communication, and external communication occurs with the end processing elements.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2023-2030
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• 2010

In this paper, we present research results of developing high performance scan conversion unit and implementing it on FPGA chip. To increase performance of scan conversion unit, we propose an architecture of scan converter that is a SIMD architecture and uses tile-based traversing method. The proposed scan conversion unit can operate about 124Mhz clock frequency on Xilinx Vertex4 LX100 device. To verify the scan conversion unit, we also develop shader unit, texture mapping unit and $240{\times}320$ color TFT-LCD controller to display outputs of the scan conversion unit on TFT-LCD. Because the scan conversion unit implemented on FPGA has 311Mpixels/sec pixel rate, it is applicable to desktop pc's 3d graphics system as well as mobile 3d graphics system needing high pixel rates.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1109-1112
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• 1998

In this paper, we propose a new architecture of the PN code acquistion system which has some shared blocks in order to reduce the hardware complexity. The proposed system has an energy calculation block which is shared by two active correlators. Our system is designed suitable for IS-95 based CDMA PCS. The new architecture was designed and simulated using VHDL. Also, We implemented it with Altera FPGA, and verified our system. The gate count is about 7,500. Our proposed architecture is also useful for multi-carrier system which uses the multiple searcher.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.142-151
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• 1996

This paper presents a new symmetrical routing architecture for FPGA and an efficient routing algorithm for the architecture. The routing architecture adopts the segmented wires and the improved switch modules. Segmetned wires construct routing channels which pass through the chip in vertical and horizontal directions. To maximize the utility of a track, a track in each switch module can be separated in two part using a programmable switch to route two different net. The proposed routing algorithm finds all assignable tracks for a given net and selects the best track from assignable tracks to minimize the number of programmable switches and the unused portion of the wire segments. In order to stabilize the perfomrance of the algorithm, the routing order is defined by weighted sum of the number of wire segment, the length of wire segmetn, and the number of pin. Experimental results show that routability is improved dramatically and the number of crossing switches are reduced about 40% compared with the previous works.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.12-18
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• 1997

An efficient synthesis method of cellular architecture FPgA is proposed in this paper. To generate a logical representation called complex term which is to be directly mapped onto the cellular architecture FPGA, and SO or ESOP minimization tool was used in previous methods. Instead, we use a logic function transformed into BDD (binary decision diagram) in the actual generation of the complex temrs. In this process it estimates the cost(i.e. the number of complex terms) for three branches, 0-branch and 1-branches. This process is continued over the whole BDD to do such computation, and we observed that the number of complex terms has been reduced compared to the previous results.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.115-121
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• 2023

RISC-V is an open-source instruction set architecture, and anyone can freely design and implement a RISC-V microprocessor. This paper designes and simulates the RISC-V architecture, synthesizing it in FPGA and verifying it using logic analyzer (ILA). RISC-V core is written in SystemVerilog, which has efficient design and high reusability, and can be used in various application fields. The RISC-V core is implemented as hardware by synthesizing it on the Ultra96-V2 FPGA board using Vivado, and the accuracy and operation of the design are verified through Integrated Logic Analyzer(ILA). As a result of the experiment, it is confirmed that the designed RISC-V core performs the expected operation, and these results can contribute to the design and verification of RISC-V based systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12A
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• pp.1261-1269
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• 2008

This paper presents an implementation of the Network Capable Application Processor (NCAP) and the Wireless Transducer Interface Module (WTIM) architectures based on the new IEEE P1451.5 standard. Proposed architecture is implemented using a computer for NCAP, an FPGA board, a sensor board and two radio modules, which communicate through the ZigBee wireless communication technology between the NCAP and the WTIM based on the IEEE 1451.0 and the IEEE 1451.5 interfaces. In this paper, two experiments has been done to verify operations of proposed architecture. From the experimental results, we verify that the proposed architecture performs the wireless sensor communication functions efficiently.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.287-294
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• 2010

MB-OFDM UWB system will adopt LDPC codes to enhance the decoding performance with higher data rates. In this paper, we will consider algorithm and architecture of the LDPC codes in MB-OFDM UWB system. To suggest the hardware efficient LDPC decoder architecture, LLR(log-likelihood-ration) calculation algorithms and check node update algorithms are analyzed. And we proposed the architecture of LDPC decoder for the high throughput application of Wimedia UWB. We estimated the feasibility of the proposed architecture by implementation in a FPGA. The implementation results show our architecture attains higher throughput than other result of QC-LDPC case. Using this architecture, we can implement LDPC decoder for high throughput transmission, but it is 0.2dB inferior to the BP algorithm.

• The KIPS Transactions:PartB
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• v.13B no.3 s.106
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• pp.223-230
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• 2006

A window-based image processing is an elementary part of image processing area. Because window-based image processing is computationally intensive and data intensive, it is hard to perform ail of the operations of a window-based image processing in real-time by using a software program on general-purpose computers. This paper proposes a parallel hardware architecture that can perform a window-based image processing in real-time using FPGA(Field Programmable Gate Array). A dynamic threshold circuit and a local histogram equalization circuit of the proposed architecture are designed using VHDL(VHSIC Hardware Description Language) and implemented with an FPGA. The performances of both implementations are measured.