• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.670-673
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• 2008

Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP verified doubly in view of hardware structure together with algorithmic verification, was implemented on the Altera Excalibur FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.129-139
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• 2013

In this paper, we proposed a new hardware architecture for calculating digital holograms at high speed, and verified it with field programmable gate array (FPGA). First, we rearranged memory scheduling and algorithm of computer generated hologram (CGH), and then introduced pipeline technique into CGH process. Finally we proposed a high-performance CGH processor. The hardware was implemented for the target of FPGA, which calculates a unit region of holograms, and it was verified using a hardware environment of NI Inc. and a FPGA of Xilinx Inc. It can generate a hologram of $16{\times}16$ size, and it takes about 4 sec for generating a hologram of a $1,024{\times}1,024$ size, using 6K point sources.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12B
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• pp.1175-1182
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• 2010

In this paper, we implemented a digital circuit which is targeted on FPGA for estimating azimuth information and distance between aircraft and ground station. All functions for signal processing of TACAN were integrated into a FPGA. The proposed hardware consists of input interface, register file, decoder, signal generator and main controller block. The designed hardware includes a function to generating pulse pair group for azimuth information, a function to responding the interrogation of aircraft for estimating distance between aircraft and ground station, and a function to provide ID information of ground station. The proposed hardware was implemented with FPGA chipset of ALTERA and occupied with 7,071 logic elements.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1553-1557
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• 2004

A real-time processing system for embedded hardware genetic algorithm is suggested. In order to operate basic module of genetic algorithm in parallel, such as selection, crossover, mutation and evaluation, dual processors based architecture is implemented. The system consists of two Xscale processors and two FPGA with evolvable hardware, which enables to process genetic algorithm efficiently by distributing the computational load of hardware genetic algorithm to each processors equally. The hardware genetic algorithm runs on Linux OS and the resulted chromosome is executed on evolvable hardware in FPGA. Furthermore, the suggested architecture can be extended easily for a couple of connected processors in serial, making it accelerate to compute a real-time hardware genetic algorithm. To investigate the effect of proposed approach, performance comparisons is experimented for an typical computation of genetic algorithm.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.93-97
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• 2005

This paper proposes a design of stepper motor control in microstep driven mode using FPGA (Field Programmable Gate Array) for hardware implementation. The methods to drive stepper motor in microstep excitation mode are to control of the controlling currents in each phase windings of stepper motor with reference signals. These reference signals are used for controlling the current levels, the required variation of current levels with rotor position can be obtained from the ideal linear or sinusoidal approximations to the static torque-displacement ($T-{\theta}$) characteristic curve. In addition, the hardware implementation of stepper motor controller can be designed uses VHDL (Very high speed integrated circuits Hardware Description Language) and synthesis using an Altera FPGA, FLEX10K family, EPF10K20RC240-4 device as target technology and use MAX+PlusII program for overall development. A multi-stack variable-reluctance stepper motor of Sanyo Denki is used in the experiments.

• International Journal of Control, Automation, and Systems
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• v.1 no.2
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• pp.252-256
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• 2003

A biped robot should be designed to be an effective mechanical structure and have smaller hardware system if it is to be a stand-alone structure. This paper shows the design methodology of a biped robot controller using FPGA(Field Programmable Gate Array). A hardware system consists of DSP(Digital Signal Processor) as the main CPU, and FPGA as the motor controller. By using FPGA, more flexible hardware system has been achieved, and more compact and simple controller has been designed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.689-691
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• 2012

In this study, a MDDI protocol packet generation method that is implemented in software is proposed. MDDI protocol is used widely for display device. In this study, MDDI protocol packets are generated by software within micro processor. This method needs minimum hardware configuration. For implementation of this method, we design a hardware platform with a high performance microprocessor and a FPGA. The packets generated by software within microprocessor is converted into LVDS signals, and transmitted by hardware within FPGA.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.298-306
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• 2011

In this paper, the RUNCODE encoder hardware IP was designed and implemented for symbol ID code length encoding, which is one of major modules of JBIG2 encoder for FAX. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the hardware generation and synthesis of VHDL code. The synthesized hardware was downloaded to Virtex-4 FX60 FPGA on ML410 development board. The synthesized hardware utilizes 13% of total slice of FPGA. Using Active-HDL tool, the hardware was verified showing normal operation. Compared with the software operating using Microblaze cpu on ML410 board, the synthesized hardware was better in operation time. The improvement ratio of operation time between the synthesized hardware and software showed about 40 times faster than software only operation. The synthesized H/W and S/W module cooperated to succeed in compressing the CCITT standard document.

• Smart Media Journal
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• v.11 no.2
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• pp.70-76
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• 2022

IoT application development using a cloud server causes problems such as data transmission and reception delay, network traffic, and cost for real-time processing support in network connected hardware. To solve this problem, edge cloud-based platforms can use neuromorphic hardware to enable fast data transfer. In this paper, we propose a model optimization method for supporting spiking neural networks on FPGA hardware. We focused on auto-adjusting network model parameters optimized for neuromorphic hardware. The proposed method performs optimization to show higher performance based on user requirements for accuracy. As a result of performance analysis, it satisfies all requirements of accuracy and showed higher performance in terms of expected execution time, unlike the naive method supported by the existing open source framework.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.145-151
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• 2015

We describe in this paper a hardware-based improvement scheme of a real-time automatic speech recognition (ASR) system with respect to speed by designing a parallel feature extraction algorithm on a Field-Programmable Gate Array (FPGA). A computationally intensive block in the algorithm is identified implemented in hardware logic on the FPGA. One such block is mel-frequency cepstrum coefficient (MFCC) algorithm used for feature extraction process. We demonstrate that the FPGA platform may perform efficient feature extraction computation in the speech recognition system as compared to the generalpurpose CPU including the ARM processor. The Xilinx Zynq-7000 System on Chip (SoC) platform is used for the MFCC implementation. From this implementation described in this paper, we confirmed that the FPGA platform is approximately 500× faster than a sequential CPU implementation and 60× faster than a sequential ARM implementation. We thus verified that a parallelized and optimized MFCC architecture on the FPGA platform may significantly improve the execution time of an ASR system, compared to the CPU and ARM platforms.