Journal of Korea Society of Digital Industry and Information Management (디지털산업정보학회논문지)

Korea Society of Digital Industry and Information Management (디지털산업정보학회)
권호 표지

Hardware Implementation for High-Speed Generation of Computer Generated Hologram

컴퓨터 생성 홀로그램의 고속 생성을 위한 하드웨어 구현

  • Published : 2013.03.30
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Abstract

In this paper, we proposed a new hardware architecture for calculating digital holograms at high speed, and verified it with field programmable gate array (FPGA). First, we rearranged memory scheduling and algorithm of computer generated hologram (CGH), and then introduced pipeline technique into CGH process. Finally we proposed a high-performance CGH processor. The hardware was implemented for the target of FPGA, which calculates a unit region of holograms, and it was verified using a hardware environment of NI Inc. and a FPGA of Xilinx Inc. It can generate a hologram of $16{\times}16$ size, and it takes about 4 sec for generating a hologram of a $1,024{\times}1,024$ size, using 6K point sources.

Keywords

References

  1. T. Motoki, H. Isono, and I. Yuyama, "Present Status of Three-Dimensional Television Research," Proc. IEEE 83(7), July, 1995, pp.1009-1021. https://doi.org/10.1109/5.390119
  2. J. K. Chung and M. H. Tsai, Three-Dimensional Holographic Imaging, John Wiley & Sons, Inc., 2002.
  3. P. Hariharan, Basics of Holography, Cambridge University Press, May, 2002.
  4. Mark Lucente, "Interfactive Computation of Holograms Using a Look-up Table," Journal of Electronic Imaging, vol. 2, #1, Jan. 1993, pp. 28-34. https://doi.org/10.1117/12.133376
  5. H. Yoshikawa, S. Iwase, and T. Oneda, "Fast Computation of Fresnel Holograms employing Differences," Proceeding of SPIE, vol. 3956, 2000.
  6. T. Shimobaba, T. Ito, "An efficient computational method suitable for hardware of computer-generated hologram with phase computation by addition," Computer Physics Communications, vol. 138, 2001, pp.44-52. https://doi.org/10.1016/S0010-4655(01)00189-8
  7. T. Ito, N. Masuda, K. Yoshimura, A. Shiraki, T. Shimobaba, and T. Sugie, "Special-Purpose computer HORN-5 for a real-time electroholography," Optics Express, Vol. 13, No. 6, March 2005.
  8. Y. Ichihashi, H. Nakayama, T. Ito, N, Masuda, T. Shimobaba, A, Shiraki, and T. Sugie, "HORN-6 special-purpose clustered computing system for electroholography," Optics Express, vol. 17, no. 16, Aug, 2009, pp.13895-13903. https://doi.org/10.1364/OE.17.013895
  9. Y. -H. Seo, H. -J. Choi, J. -S. Yoo, and D. -W. Kim, "An architecture of a high-speed digital hologram generator based on FPGA," Journal of Systems Architecture, Vol. 56, Dec. 2009, pp.27-37.
  10. 이승학, 김경혼, 안치영, 최승원, "GPU를 이용한 SDR 시스템용 LTE MIMO 기지국 기능 구현," 디지털산업정보학회 논문지, 제8권, 제4호, 2012, pp. 91-98.
  11. 김태현, 이현석, 최승원, "SDR 시스템에서 GPU를 사용한 Lattice Reduction-aided 검출기 구현," 디지털산업정보학회 논문지, 제7권, 제3호, 2011, pp. 55-61.
  12. Y. -H. Seo, H. -J. Choi, J. -S. Yoo, and D. -W. Kim, "A New Parallelizing Algorithm and Cell-based Hardware Architecture for High-speed Generation of Digital Hologram," Journal of Systems Architecture, Vol. 16, Jan. 2011, pp. 54-63.
  13. Y. -H. Seo, Y. -H. Lee, J. -S. Yoo, and D. -W. Kim, "Hardware architecture of highperformance digital hologram generator on the basis of a pixel-by-pixel calculation scheme", Applied optics, Vol 51. No. 18, Jun. 2012, pp.4003-4012. https://doi.org/10.1364/AO.51.004003