• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1185-1194
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• 1997

It is necessary to control the frame memory to capture, edit and display images. This paper presents the free-scale image capture processor size of which is user-defined, compared to the conventional image capture processor size of which is fixed 1/2, 1/4 and full size. User-defined scale data is fed into this system, which generates the gating pulses and gates the inputted image data. This system also controls the 4M DRAM instead of frame meamory. And stored gated image data are displayed on the TV monitor. We designed the scalable image capture parts and DRAM controller with ACTEL FPGAs, simulated the circuits with Viewlogic and fusing ACTEL A1020B chips. We confirmed the whole operation with beadboard which composed of "Philips TV Chipset" and designed FPGA chips.PGA chips.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.784-789
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• 2007

This paper presents an implementation of a new type of architecture to improve an overflow problem on the network buffer. Each receiver channel of network system stores the message in its own buffer. If some receiver channel receives many messages, buffer overflow problem may occur for the channel. This paper proposes a network controller that implements a receiver channel with shared-memory to save all of the received messages from the every incomming channels. The proposed architecture is applied to ARINC-429, a real-time control network for commercial avionics system. For verifying performance of the architecture, ARINC-429 controller is designed using a SOPC platform, designed by Verilog and targeted to Xilinx Virtex-4 with a built-in PPC405 core.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1482-1490
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• 2001

디지털 통신 시스템 및 신호처리 회로의 핵심 연산블록으로 사용될 수 있는 복소수 승산기 코어의 파라미터화된 소프트 IP (Intellectual Property)를 설계하였다. 승산기는 응용분야에 따라 요구되는 비트 수가 매우 다양하므로, 승산기 코어 IP는 비트 수를 파라미터화하여 설계하는 것이 필요하다. 본 논문에서는 복소수 승산기의 비트 수를 파라미터화 함으로써 사용자의 필요에 따라 승수와 피승수를 8-b∼24-b 범위에서 2-b 단위로 선택하여 사용할 수 있도록 하였으며, GUI 환경의 코어 생성기 PCMUL_GEN는 지정된 비트 크기를 갖는 복소수 승산기의 VHDL 모델을 생성한다. 복소수 승산기 코어 IP는 redundant binary (RB) 수치계와 본 논문에서 제안하는 새로운 radix-4 Booth 인코딩/디코딩 회로를 적용하여 설계되었으며, 이를 통해 기존의 방식보다 단순화된 내부 구조와 고속/저전력 특성을 갖는다. 설계된 IP는 Xilinx FPGA로 구현하여 기능을 검증하였다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.4
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• pp.265-276
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• 2004

Genetic Algorithm(GA), that is shown stable performance to find an optimal solution, has been used as a method of solving large-scaled optimization problems with complex constraints in various applications. Since it takes so much time to execute a long computation process for iterative evolution and adaptation. In this paper, a hardware-based adaptive GA was proposed to reduce the serious computation time of the evolutionary process and to improve the accuracy of convergence to optimal solution. The proposed GA, based on steady-state model among continuos generation model, performs an adaptive mutation process with consideration of the evolution flow and the population diversity. The drawback of the GA, premature convergence, was solved by the proposed adaptation. The Performance improvement of convergence accuracy for some kinds of problem and condition reached to 5-100% with equivalent convergence speed to high-speed algorithm. The proposed adaptive GAP(Genetic Algorithm Processor) was implemented on FPGA device Xilinx XCV2000E of EHW board for face recognition.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.152-154
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• 2005

This paper proposes the new subfield method to erase reverse gray levels and low gray level contour in AC plasma display panel(PDP). In the conventional method, it is supposed that output luminance levels of a PDP increase regularly. But actual output luminance levels of a PDP increase irregularly. Therefore, conventional methods are unable to effectively reduce low gray-level contours and reverse gray levels. Accordingly, a new subfield method is applied to improve the low gray-level expression in PDP. Conclusively this paper clear proof that a new subfield method can suppress low gray-level contours and reverse gray levels more effectively than conventional methods.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.78-80
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• 2005

The pattern recognition of automobile and parking line for the automatic car parking system was processed based on statistical method for reducing the processing time. The command of driving for parking at the vacant parking lot was transmitted from processor to motor driven actuator using direct sequence spread spectrum communication, which enables the multiple transmission in CAN(controller area network). The test-bed which has CCD camera, processor, radio transceiver and FPGA was implemented and demonstrated to be operated well.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.4
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• pp.371-376
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• 2004

Distributed Network Protocol Version 3.0 (DNP3.0) is the communication protocol developed for the interoperability between a RTU and a central control station of SCADA in the power utility industry. In this paper DNP3.0 is implemented by using HDL with FPGA and C program on Hitachi H8/532 processor. DNP3.0 is implemented from physical layer to network layer in hardware level to reduce the computing load on a CPU. Finally, the ASIC for DNP3.0 has been manufactured from Hynix Semiconductor. The commercial feasibility of the hardware through the communication test with ASE2000 and DNP Master Simulator is performed. The developed protocol becomes one of IP, and can be used to implement SoC for the terminal device in SCADA systems. Also, the result can be applicable to various industrial controllers because it is implemented in HDL.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.83-86
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer operation of a new video coding standard H.264/JVT. We describe the algorithm to derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Altera FPGA and also by ASIC synthesis using Samsung 0.18 ${\mu}{\textrm}{m}$ CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1, 300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.102-105
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• 1999

AAL type 2 provides for the bandwidth efficient transmission of low bit rate, short and variable packets in delay sensitive application. The service object for these networks ranges from POTS to multimedia conference. In this paper, we present one possible architecture which common part sublayer for new AAL type 2. The proposed CPS function has been achieved with on a FPGA The proposed architecture is faithful to the standardization of ITU-T and ATM-forum recommendation The proposed architecture applies to variable packet length from architecture CODECs for cellular network.. It's maximum process capability is 155Mbps with 256 CIDs. The architecture has sync./async. interface to application block and UTOPIA interface is used for physical layer interface.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.33-38
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• 2006

The ATE driver to test a high speed semiconductor chip is designed by using general logic drivers instead of dedicated pin drivers. We have proposed a structure of general logic drivers using FPCA and assured its correct operation by EDA tool simulation. PCB circuit was implemented and Altera FPGA chip was programmed using DDR I/O library. On the PCB, it is necessary to place two resistors connected output drivers near to the output pin to adjust an impedance matching. We confirmed that the measured results agree with the simulated values within 5% errors at room temperature for the input signals with 800Mbps data transfer rate and 1.8V operating voltage.