The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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Implementation of the Multi-Channel Network Controller using Buffer Sharing Mechanism

버퍼공유기법을 사용한 멀티채널 네트워크 컨트롤러 구현

  • 이태수 (인하대학교 정보통신공학과) ;
  • 박재현 (인하대학교 정보통신공학과)
  • Published : 2007.04.01
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Abstract

This paper presents an implementation of a new type of architecture to improve an overflow problem on the network buffer. Each receiver channel of network system stores the message in its own buffer. If some receiver channel receives many messages, buffer overflow problem may occur for the channel. This paper proposes a network controller that implements a receiver channel with shared-memory to save all of the received messages from the every incomming channels. The proposed architecture is applied to ARINC-429, a real-time control network for commercial avionics system. For verifying performance of the architecture, ARINC-429 controller is designed using a SOPC platform, designed by Verilog and targeted to Xilinx Virtex-4 with a built-in PPC405 core.

Keywords

References

  1. Peter Magnusson, 'Evaluating Xilinx MicroBlaz for Network SoC Applications', Master's Thesis in Computer Engineering, pp. 30-31, 2004
  2. S. Andrew, Tanenbaum, Computer Networks 4nd, Prentice Hall PTR, pp 506-510, 2003
  3. M. Mobasseri, V.P.M Leung, 'A new buffer management scheme for multimedia terminals in broadband satellite networks', Proceedings of the 35th Hawaii International Conference on System Sciences, Volume 5, pp, 2786-2790, 2002
  4. M. Alisafaee, S.M Fakhraie, M. Tehranipoor, 'Architecture of an embedded queue management engin for high-speed network devices', 48th Midwest Symposium on Circuits and Systems, Vol.2, pp. 1907-1910, 2005
  5. Y.-M Joo, N. McKeown, 'Doubling memory bandwidth for network buffers', INFOCOM '98. Conference of the IEEE Computer and Communications Societies, Vol 2, pp.808-815, 1998
  6. S.M Qasim, S.A Abbasi, 'FPGA implementation of a single-channel HDLC Layer-2 protocol transmitter using VHDL' Proceedings of the 15th International Conference on Microelectronics, pp. 265-268, 2003
  7. Po-Tsang Huang, Wei Hwang, '2-level FIFO architecture design for switch fabrics in network-on-chip', in ISCAS'06, pp. 4863-4866, 2006
  8. ARINC Specification 429 PART 1-17, ARINC Inc., pp. 1-3, 2004
  9. Len Buckwalter, AVIONICS DATABUSES 2nd, Avionics Communications Inc., pp. 10.4-5, 2003
  10. Virtex-4 User Guide, Xilinx Inc., 2006
  11. OPB IPIF(v3.01c), Xilinx Inc., 2005
  12. Virtex-4 FX12 Mini Module User Guide, Memec Inc., 2005