• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.906-911
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• 2008

This paper designed Simulik Model to cancel the carrier frequency offset in OFDM using CORDIC Algorithm and evaluated its performance. And Simulink Model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model is error free by CORDIC when offset frequency is lower than $10^5MHz$. Also, we verified the performance through Hardware Co-simulation with Xilinx Spartan3 xc3s1000 fg676-4 Target Device, and timing analysis and resource estimation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.306-313
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• 2007

In this paper, we efficiently implemented turbo code algorithm in FPGA H/W(hardware) resource. The used turbo code algorithm has the characteristics; the size of constraint is 3, encoder type is 1/3, the size of random interleaver is 2048. The proposed H/W consists of MAP block for calculating alpha and delta using delta value, storing buffer for each value, multiplier for calculating lamda, and lamda buffer. The proposed algorithm and H/W architecture was verified by C++ language and was designed by VHDL. Finally the designed H/W was programmed into FPGA and tested in wireless communication environment for field availability. The target FPGA of the implemented H/W is VERTEX4 XC4VFX12-12-SF363 and it is stably operated in 131.533MHz clock frequency (7.603ns).

• The Journal of Korean Institute of Next Generation Computing
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• v.15 no.2
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• pp.7-16
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• 2019

Neural networks can be implemented in variety of ways, and specialized chips is being developed for hardware improvement. In order to apply such neural networks to wearable devices, the compactness and the low power operation are essential. In this point of view, a suitable implementation method is a digital circuit design using field programmable gate array (FPGA). To implement this system, the learning algorithm which takes up a large part in neural networks must be implemented within FPGA for better performance. In this paper, a back propagation algorithm among various learning algorithms is implemented using FPGA, and this neural network is verified by OR gate operation. In addition, it is confirmed that this neural network can be used to analyze various users' bio signal measurement results by learning algorithm.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.9
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• pp.789-794
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• 2014

The FPGA is used to the high speed digital satellite communication on the Digital Signal Process Unit of the next generation GEO communication satellite. The high capacity FPGA has the high power dissipation and it is difficult to satisfy the derating requirement of temperature. This matter is the major factor to degrade the equipment life and reliability. The thermal control at the equipment level has been worked through thermal conduction in the space environment. The FPGA of CCGA or BGA package type was mounted on printed circuit board, but the PCB has low efficient to the thermal control. For the FPGA heat dissipation, the heat sink was applied between part lid and housing of equipment and the performance of heat sink was confirmed via thermal vacuum test under the condition of space qualification level. The FPGA of high power dissipation has been difficult to apply for space application, but FPGA with heat sink could be used to space application with the derating temperature margin.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2002.06a
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• pp.87-87
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• 2002

본 논문에서는 모듈성과 확장성을 갖는 시스톨릭 어레이 정렬기(Systolic Array Sorter)의 구현에 대하여 기술한다. 정규순환방정식으로 표현된 정렬(sorting)알고리즘으로부터 1차원 평면 시스톨릭 어레이를 유도한 후 유도된 정렬 시스톨릭 어레이를 RTL 수준에서 VHDL로 모델링 하여 동작을 검증하였다. 검증된 시스톨릭 어레이 정렬기는 synopsys hynix-0.35$\mu\textrm{m}$ 셀 라이브러리와 FPGA s40pq240칩을 사용하여 합성 및 구현되었다.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.197-200
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• 2003

본 논문에서는 IEEE 802.11a 무선 LAN 용 CODEC 회로를 설계하고, VHDL 코딩과 FPGA에 의한 회로설계 검증에 관해 기술한다. IEEE 802.lla WLAN CODEC의 구조는 크게 데이터 보호를 위한 스크램블러/디스크램블러, 채널 에러에 대한 정보보호를 위한 Convolutional 부호기와 Viterbi 복호기로 구성된 채널 코덱, 그리고 연집에러를 랜덤 에러로 변화시키는 인터리버/디인터리버로 구성된다. 본 논문에서는, 이와 같은 CODEC의 각 부분을 하드웨어로 구현하기 위한 새로운 회로구성을 제안하고, 그 성능을 VHDL 코딩에 의한 시뮬레이션과 FPGA에 의한 하드웨어 검증 결과를 제시한다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.442-444
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• 2003

본 논문에서는 IEEE 802.113 무선 LAN 용 CODEC 회로를 설계하고, VHDL 코딩 과 FPGA에 의한 회로설계 검증에 관해 기술한다. IEEE 802.11a WLAN CODEC의 구조는 크게 데이터 보호를 위한 스크램블러/디스크램블러, 채널 에러에 대한 정보보호를 위한 Convolutional 부호기와 Viterbi 복호기로 구성된 채널 코덱, 그리고 연집에러를 랜덤 에러로 변화시키는 인터리버/디인터 리버로 구성된다. 본 논문에서는, 이와 같은 CODEC의 각 부분을 하드웨어로 구현하기 위한 새로운 회로구성을 제안하고, 그 성능을 VHDL 코딩에 의한 시뮬레이션과 FPGA에 의한 하드웨어 검증 결과를 제시한다.

• Journal of Satellite, Information and Communications
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• v.4 no.1
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• pp.36-44
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• 2009

The key technologies of GNSS receiver for GNSS sensor station are under development as a part of a GNSS ground station in ETRI. This paper presents the GNSS receiver implementation and signal processing result which is implemented based on FPGA to process the Galileo E1 and E5 signal. To verify the working and performance for GNSS receiver which is implemented based on FPGA, live signal received from GIOVE-B which is second test satellite is used. We gather GIOVE-B signal by using prototyping antenna and RF/IF units including IF-component. To verify Galileo E1 and E5 signal processing function from GIOVE-B, FPGA based signal processing module is implemented as a prototyping hardware board.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.368-377
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• 2011

This paper explains the hardware structure of SURF(Speeded Up Robust Feature) based feature point extractor and its FPGA verification result. SURF algorithm produces novel scale- and rotation-invariant feature point and descriptor which can be used for object recognition, creation of panorama image, 3D Image restoration. But the feature point extraction processing takes approximately 7,200msec for VGA-resolution in embedded environment using ARM11(667Mhz) processor and 128Mbytes DDR memory, hence its real-time operation is not guaranteed. We analyzed integral image memory access pattern which is a key component of SURF algorithm to reduce memory access and memory usage to operate in c real-time. We assure feature extraction that using a Vertex-5 FPGA gives 60frame/sec of VGA image at 100Mhz.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.9
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• pp.896-903
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• 2011

In this paper, a co-design method for JPEG2000 video compression system using DSP and FPGA is presented. By profiling the complexity of JPEG2000 algorithm, it is noticed that a MQ-coder is the most complex part. Thus, we implement the MQ-coder on FPGA for the parallel processing using VHDL to reduce the complexity. In order to verify the performance of the MQ-coder, JBIG2 standard test vector and images are used. The experimental results show that the proposed MQ-coder enhances the processing time approximately 3 times compared with the previous software MQ-coder.