References
- J. Schmidhuber, "Deep learning in neural networks: An overview," Neural Networks, vol. 61, pp. 85-117, Nov. 2015. https://doi.org/10.1016/j.neunet.2014.09.003
- S. Gupta, A. Agrawal, K. Gopalakrishnan, and P. Narayanan, "Deep learning with limited numerical precision," in International Conference on Machine Learning, 2015, pp. 1737-1746.
- M. Oquab, L. Bottou, I. Laptev, and J. Sivic, "Learning and transferring mid-level image representations using convolutional neural networks," in Proceedings of the IEEE conference on Computer Vision and Pattern Recognition, 2014, pp. 1717-1724.
- F. Akopyan, "Design and tool flow of IBM's TrueNorth: An ultra-low power programmable neurosynaptic chip with 1 million neurons," in Proceedings of the 2016 on International Symposium on Physical Design, 2016, pp. 59-60.
- A. G. Andreou, A. A. Dykman, K. D. Fischl, G. Garreau, D. R. Mendat, G. Orchard, A. S. Cassidy, P. Merolla, J. Arthur, R. A.-Icaza, B. L. Jackson, and D. S. Modha, "Real-time sensory information processing using the TrueNorth neurosynaptic system," in IEEE International Symposium on Circuits and Systems, 2016, pp. 2911-2920.
- R. Wang, C. S. Thakur, G. Cohen, T. J. Hamilton, J. Tapson, and A. Schaik, "Neuromorphic Hardware Architecture Using the Neural Engineering Framework for Pattern Recognition," IEEE Trans. on Biomedical Circuits and Systems, vol. 11, no. 3, pp. 574-584, Jun. 2017. https://doi.org/10.1109/TBCAS.2017.2666883
- J. Park, T. Yu, S. Joshi, C. Maier, and G. Cauwenberghs, "Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems," IEEE Trans. Neural Networks and Learning Systems, vol. 28, no. 10, pp. 2408-2422, Oct. 2017. https://doi.org/10.1109/TNNLS.2016.2572164
- G. Indiveri and S.-C. Liu, "Memory and Information Processing in Neuromorphic Systems," Proceedings of the IEEE, vol. 10, no. 8, pp. 1379-1397, Aug. 2015.
- S. Furber, "Large-scale neuromorphic computing systems," Journal of Neural Engineering, vol. 13, p.051001, Aug. 2016. https://doi.org/10.1088/1741-2560/13/5/051001
- A. Yousefzadeh, T. Masquelier, T. SerranoGotarredona, and B. Linares-Barranco, "Hardware implementation of convolution STDP for on-line visual feature learning," in IEEE International Symposium on Circuits and Systems, 2017, pp. 1-4.
- S. R. Kheradphsheh, M. Ganjtabesh, S. J. Thorpe, and T. Masquelier, "STDP-based spiking deep convolutional neural networks for object recognition," Neural Networks, vol. 99, pp. 56-67, Mar. 2018. https://doi.org/10.1016/j.neunet.2017.12.005
- G. Srinivasan and A. Sengupta, "Magnetic Tunnel Junction Based Long-Term Short-Term Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning," Scientific Reports, vol. 6, p. 29545, Jul. 2016. https://doi.org/10.1038/srep29545
- G. K. Chen, R. Kumar, H. E. Sumbul, P. C. Knag, and R. K. Krishnamurthy, "A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS," IEEE Journal of Solid-State Circuits, vol. 54, no. 4, pp. 992-1002, Apr. 2019. https://doi.org/10.1109/JSSC.2018.2884901
- A. Nagabandi, G. Kahn, R. S. Fearing, and S. Levine, "Neural Network Dynamics for Model-Based Deep Reinforcement Learning with Model-Free Fine-Tuning," in IEEE International Conference on Robotics and Automation, 2018, pp. 7579-7586, Aug. 2016.
- I. Bello, B. Zoph, V. Vasudevan, and Q. V. Le, "Neural optimizer search with reinforcement learning," in Internation Conference on Machine Learning, 2017, pp. 459-468.