• Journal of Korea Multimedia Society
• /
• v.16 no.4
• /
• pp.483-492
• /
• 2013

SURF is an algorithm which extracts feature points and generates their descriptors from input images, and it is being used for many applications such as object recognition, tracking, and constructing panorama pictures. Although SURF is known to be robust to changes of scale, rotation, and view points, it is hard to implement it in real time due to its complex and repetitive computations. Using 3.3 GHz Pentium, in our experiment, it takes 240ms to extract feature points and create descriptors in a VGA image containing about 1,000 feature points, which means that software implementation cannot meet the real time requirement, especially in embedded systems. In this paper, we present a hardware architecture that can compute the SURF algorithm very fast while consuming minimum hardware resources. Two key concepts of our architecture are parallelism (for repetitive computations) and efficient line memory usage (obtained by analyzing memory access patterns). As a result of FPGA synthesis using Xilinx Virtex5LX330, it occupies 101,348 LUTs and 1,367 KB on-chip memory, giving performance of 30 frames per second at 100 MHz clock.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.10
• /
• pp.2380-2388
• /
• 2015

A hardware implementation of MOD(moving object detection) algorithm using EGML(effective Gaussian mixture learning)- based background subtraction to detect moving objects in video is described. Some approximations of EGML calculations are applied to reduce hardware complexity, and pipelining technique is adopted to improve operating speed. The MOD processor designed in Verilog-HDL has been verified by FPGA-in-the-loop verification using MATLAB/Simulink. The MOD processor has 2,218 slices on the Virtex5-XC5VSX95T FPGA device and its throughput is 102 MSamples/s at 102 MHz clock frequency. Evaluation results of the MOD processor for 12 images in the IEEE CDW-2012 dataset show that the average recall value is 0.7631, the average precision value is 0.7778 and the average F-measure value is 0.7535.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.10
• /
• pp.2373-2379
• /
• 2015

COMS(Communication, Ocean and Meteorological Satellite), the first Korean geostationary meteorological satellite, provides free meteorological information through HRIT/LRIT(High/Low Rate Information Transmission) service. This work presents the development of data receiver circuit that is essential to the implementation of a low-cost meteorological information receiver system. The data receiver circuit processes the data units according to the specification of physical layer and data link layer of HRIT/LRIT service. For this purpose, the circuit consists of a Viterbi decoder, a sync. word detector, a derandomizer, a Reed-Solomon decoder and so on. The circuit also supports PCI express interface to pass the information data on to the host PC. The circuit was implemented on an FPGA(field programmable gate array) and its function was verified through simulations and hardware implementation.

• Journal of the Korea Society of Computer and Information
• /
• v.17 no.4
• /
• pp.11-18
• /
• 2012

Deep packet inspection which perform pattern matching to search for malicious patterns in the packet is most computationally intensive task. Hardware-based pattern matching is required for real-time packet inspection in high-speed network. In this paper, we have designed and implemented network intrusion detection hardware as a Microblaze-based SoC using Virtex-6 FPGA, which capture the network input packet, perform hardware-based pattern matching for patterns in the Snort rule, and provide the matching result to the software. We verify the operation of the implemented system using traffic generator and real network traffic. The implemented hardware can be used in network intrusion detection system operated in wire-speed.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.46 no.2
• /
• pp.57-64
• /
• 2009

This paper presents the hardware implementation of the pyramidal KLT(Kanade-Lucas-Tomasi) feature tracker. Because of its high computational complexity, it is not easy to implement a real-time KLT feature tracker using general-purpose processors. A hardware implementation of the pyramidal KLT feature tracker using FPGA(Field Programmable Gate Array) is described in this paper with emphasis on 1) adaptive adjustment of threshold in feature extraction under diverse lighting conditions, and 2) modification of the tracking algorithm to accomodate parallel processing and to overcome memory constraints such as capacity and bandwidth limitation. The effectiveness of the implementation was evaluated over ones produced by its software implementation. The throughput of the FPGA-based tracker was 30 frames/sec for video images with size of $720{\times}480$.

• The KIPS Transactions:PartA
• /
• v.9A no.1
• /
• pp.53-60
• /
• 2002

This paper describes a Gray Mode Graphic STN LCD drive circuit using USB interface. The drive circuit using USB interface can highly transfer image data created under PC t LCD. Hence, the LCD drive circuit doesn't use microprocessor for the convenience of users. The proposed LCD drive circuit part have been verified by simulation and by ALTERA EPF10K10TC144-3 FPGA implementation in VHDL. The USB interface part have been programmed in MS-Visual C++ 6.0. The validity and efficiency of the proposed LCD drive circuit have been verified by test board. After comparing this LCD drive circuit to specify it was verified that the developed LCD drive circuit showed good performances, such as convenience of users, low cost.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.24 no.2
• /
• pp.268-275
• /
• 2020

A lightweight hardware design of self-timed ring based true random number generator (TRNG) suitable for information security applications is described. To reduce hardware complexity of TRNG, an entropy extractor with feedback structure was proposed, which minimizes the number of ring stages. The number of ring stages of the FSTR-TRNG was determined to be a multiple of eleven, taking into account operating clock frequency and entropy extraction circuit, and the ratio of tokens to bubbles was determined to operate in evenly-spaced mode. The hardware operation of FSTR-TRNG was verified by FPGA implementation. A set of statistical randomness tests defined by NIST 800-22 were performed by extracting 20 million bits of binary sequences generated by FSTR-TRNG, and all of the fifteen test items were found to meet the criteria. The FSTR-TRNG occupied 46 slices of Spartan-6 FPGA device, and it was implemented with about 2,500 gate equivalents (GEs) when synthesized in 180 nm CMOS standard cell library.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.17 no.3
• /
• pp.166-175
• /
• 2024

In this paper, the Window-Masking Method and HAT (Hardware Attached Top) CPU SoM (System on Module) are used to improve the performance and reduce the weight of the MANET (Mobile Ad-hoc Network) network synchronization system using time division redundancy. We propose converting it into a RISC-V based soft-core MCU and mounting it on an FPGA, a hardware accelerator. It was also verified through experiment. In terms of performance, by applying the proposed technique, the synchronization acquisition range is from -50dBm to +10dBm to -60dBm to +10dBm, the lowest input level for synchronization is increased by 20% from -50dBm to -60dBm, and the detection delay (Latency) is 220ns. Reduced by 43% to 125ns. In terms of weight reduction, computing resources (48%), size (33%), and weight (27%) were reduced by an average of 36% by replacing with soft-core MCU.

• Journal of IKEEE
• /
• v.15 no.4
• /
• pp.267-273
• /
• 2011

In hardware design, its stability and reliability are important, because a hardware error can cause serious damages or disaster. To improve stability and reliability, this paper presents the implementation of the hardware verification system using the fault injection method in PC environment. This paper presents a verification platform that can verify hardware system reliably and effectively, through a process to generate faults as well as insert input signals into the actual running system environment. The verification system is configured to connect a PC with a digital I/O card, and it can transmit or receive signals from the target system, as a verifier's intention. In addition, it can generate faults and inject them into the target system. And it can be monitored by displaying the received signals from the target system to the graphical wave signals. We can evaluate its reliability by analyzing the graphical wave signals. In this paper, the proposed verification system has been applied to the FPGA firmware of a nuclear power plant control system. As a result, we found its usefulness and reliability.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.7
• /
• pp.118-127
• /
• 2010

Current TCP/IP-based Internet architecture has been used for over 30 years, however it will confront with fundamental problems due to new protocol extension limitation since communication environments will change drastically and various user requirements will be emerging in near future. To solve these problems, major countries have started Future Internet researches based on clean slate approach and they will deploy large-scale testbed to experiment and verify new functions. OpenFlow switch technology has been proposed as a new experimental technology for independent protocol that can utilized the legacy network devices and does not interfere with the production Internet traffic. Korea also started Future Internet testbed project called FIRST and OpenFlow switch with NetFPGA card will be used to deploy this testbed. To interconnect distributed testbed using OpenFlow switches, logical tunnel should be established by encapsulating MAC frame inside a unicast IP packet between OpenFlow switches because OpenFlow switches are not directly connected. In this paper, we have implemented a NetFPGA-based that performs MAC in IP tunneling between various OpenFlow switch sites implemented in domestic research network KOREN. The performance evaluation shows that the NetFPGA-based capsulator reveals better performance than the software-based tunneling and it can be utilized as a testbed for experimentation of Future Internet technologies.