• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.4
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• pp.259-267
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• 2019

An active clamp flyback (ACF) converter applies a clamp circuit and circulates the energy of leakage inductance to the input side, thereby achieving a zero-voltage switching (ZVS) operation and greatly reducing switching losses. The switching losses are further reduced by applying a gallium nitride field effect transistor (GaN-FET) with excellent switching characteristics, and ZVS operation can be accomplished under light load with boundary conduction mode (BCM) operation. Optimal design is performed on the basis of loss analysis by selecting magnetization inductance based on BCM operation and a clamp capacitor for loss reduction. Therefore, the size of the reactive element can be reduced through high-frequency operation, and a high-efficiency and high-power-density converter can be achieved. This study proposes an optimal design for a high-efficiency and high-power-density BCM ACF converter based on GaN-FETs and verifies it through experimental results of a 65 W-rated prototype.

• Journal of IKEEE
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• v.23 no.3
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• pp.811-816
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• 2019

The silicon-adsorbed oxygen(Si-O) superlattice grown by ultra high vacuum-chemical vapor deposition(UHV-CVD) was introduced as an epitaxial barrier for silicon quantum electron devices. The current-voltage (I-V) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the Si-O superlattice can serve as an epitaxially grown insulating layer as possible replacement of silicon-on-insulator(SOI). This thick barrier may be useful as an epitaxial insulating gate for field effect transistors(FETs). The rationale is that it should be possible to fabricate a FET on top of another FET, moving one step closer to the ultimate goal of future silicon-based three-dimensional integrated circuit(3DIC).

• Journal of IKEEE
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• v.24 no.4
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• pp.1167-1171
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• 2020

In this work, we proposed a graded gate-doping structure to alleviate an electric field in p-GaN gate layer in order to improve the reliability of normally-off GaN power devices. In a TCAD simulation by Silvaco Atlas, a distribution of the graded p-type doping concentration was optimized to have a threshold voltage and an output current characteristics as same as the reference device with a uniform p-type gate doping. The reduction of an maximum electric field in p-GaN gate layer was observed and it suggests that the gate reliability of p-GaN gate HFETs can be improved.

• Advances in nano research
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• v.10 no.1
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• pp.91-99
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• 2021

Silicene is an emerging two-dimensional (2D) semiconductor material which has been envisaged to be compatible with conventional silicon technology. This paper presents a theoretical study of uniformly doped silicene with aluminium (AlSi3) Field-Effect Transistor (FET) along with the benchmark of device performance metrics with other 2D materials. The simulations are carried out by employing nearest neighbour tight-binding approach and top-of-the-barrier ballistic nanotransistor model. Further investigations on the effects of the operating temperature and oxide thickness to the device performance metrics of AlSi3 FET are also discussed. The simulation results demonstrate that the proposed AlSi3 FET can achieve on-to-off current ratio up to the order of seven and subthreshold swing of 67.6 mV/dec within the ballistic performance limit at room temperature. The simulation results of AlSi3 FET are benchmarked with FETs based on other competitive 2D materials such as silicene, graphene, phosphorene and molybdenum disulphide.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.3
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• pp.264-268
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• 2022

High pressure deuterium (HPD) annealing is an advancing technology for the fabrication of modern semiconductor devices. In this work, gate-enclosed FETs are fabricated on a silicon substrate as test vehicles. After a cycle for the HPD annealing, the device parameters such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), off-state current (I_OFF), and gate leakage (I_G) were measured and compared depending on the HPD. The HPD annealing can passivate the dangling bonds at Si-SiO₂ interfaces as well as eliminate the bulk trap in SiO₂. It can be concluded that adding the HPD annealing as a fabrication process is very effective in improving device reliability, performance, and variability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.140-140
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• 2009

The Metal-ferroelectric-semiconductor (MFS) structure has superior advantages such as high density integration and non-destructive read-out operation. However, to obtain the desired electrical characteristics of an MFS structure is difficult because of interfacial reactions between ferroelectric thin film and Si substrate. As an alternative solution, the MFS structure with buffer insulating layer, i.e. metal-ferroelectric-insulator-semiconductor (MFIS), has been proposed to improve the interfacial properties. Insulators investigated as a buffer insulator in a MFIS structure, include $Ta_2O_5$, $HfO_2$, and $ZrO_2$ which are mainly high-k dielectrics. In this study, we prepared the Dy-doped $La_2O_3$ solution buffer layer as an insulator. To form a Dy-doped $La_2O_3$ buffer layer, the solution was spin-coated on p-type Si(100) wafer. The coated Dy-doped $La_2O_3$ films were annealed at various temperatures by rapid thermal annealing (RTA). To evaluate electrical properties, Au electrodes were thermally evaporated onto the surface of the samples. Finally, we observed the surface morphology and crystallization quality of the Dy-doped $La_2O_3$ on Si using atomic force microscopy (AFM) and x-ray diffractometer (XRD), respectively. To evaluate electrical properties, the capacitance-voltage (C-V) and current density-voltage (J-V) characteristics of Au/Dy-doped La2O3/Si structure were measured.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.5
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• pp.472-478
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• 2003

In this paper, a near zero If mixer was designed in cascode structure by using two single-gate FETs. Since it is driven by the second order harmonic of LO signal, a sub-harmonic cascode FET mixer has good LO-RF port isolation characteristic. In order to solve DC offset of a homodyne system, near zero If is used instead of zero If and the mixer is driven by sub-harmonic of LO signal. As RF input power was -30 dBm and LO power was 6 dBm, the designed mixer had 6.7 dB conversion gain, 8.4 dB noise figure, 31.5 dB LO-RF port isolation, -1.9 dBm lIP3 and -2.8 dBm IIP2.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.16.2-16.2
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• 2011

Graphene has attracted significant attention due to its unique characteristics and promising nanoelectronic device applications. For practical device applications, it is essential to synthesize high-quality and large-area graphene films. Graphene has been synthesized by eloborated mechanical exfoliation of highly oriented pyrolytic graphite, chemical reduction of exfoliated grahene oxide, thermal decomposition of silicon carbide, and chemical vapor deposition (CVD) on metal substrates such as Ni, Cu, Ru etc. The CVD has advantages over some of other methods in terms of mass production on large-areas substrates and it can be easily separated from the metal substrate and transferred to other desired substrates. Especially, plasma-enhanced CVD (PECVD) can be very efficient to synthesize high-quality graphene. Little information is available on the synthesis of graphene by PECVD even though PECVD has been demonstrated to be successful in synthesizing various carbon nanostructures such as carbon nanotubes and nanosheets. In this study, we synthesized graphene on $Ni/SiO_2/Si$ and Cu plate substrates with CH4 diluted in $Ar/H_2$ (10%) by using an inductively-coupled PECVD (ICPCVD). High-quality graphene was synthesized at as low as $700^{\circ}C$ with 600 W of plasma power while graphene layer was not formed without plasma. The growth rate of graphene was so fast that graphene films fully covered on substrate surface just for few seconds $CH_4$ gas supply. The transferred graphene films on glass substrates has a transmittance at 550 nm is higher 94%, indicating 1~3 monolayers of graphene were formed. FETs based on the grapheme films transferred to $Si/SiO_2$ substrates revealed a p-type. We will further discuss the synthesis of graphene and doped graphene by ICPVCD and their characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.240-250
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• 2010

Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an otherwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.