• Journal of Korean Institute of Industrial Engineers
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• v.33 no.2
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• pp.166-173
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• 2007

In this paper, we propose a model-based approach to estimating production parameters of semiconductor FAB equipment. For FAB scheduling, for example, we need to know equipment's production parameters such as flow time, tact time, setup time, and down time. However, these data are not available, and they have to be estimated from material move data such as loading times and unloading times that are automatically collected in modern automated semiconductor FAB. The proposed estimation method may be regarded as a Bayes estimation method because we use additional information about the production parameters. Namely, it is assumed that the technical ranges of production parameters are known. The proposed estimation method has been applied to a LCD FAB, and found to be valid and useful.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.692-699
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• 2008

Semiconductor research and development(R&D) fabs are very different than production fabs in many ways such as the scales of production, job priority, production methods, and performance measures. Efficient operations of R&D fabs are very important to the development of new product, process stability, high yield, and ultimately company competitiveness. This paper proposes the fab-wide scheduling method for operational optimization of the R&D fabs. Most scheduling systems of semiconductor fabs have only focused on maximizing throughput of each separated areas without considering WIP(works in process) flows of entire fab. In this paper, we proposes the a fab-wide scheduling system which schedules all lots to entire fab equipment at once. We develop the MIP(mixed integer programing) model which allocates the lots to production equipment considering many constraints of all processes and the CP(constraint programming) model which determines the sequences of the lots in the production equipment. The proposed FAB-wide scheduling model is applied to the newly constructed R&D fab. As a result, we have accomplished the system based automated job reservation, decrease of the hot lot delay, increase of the queue time satisfaction, the high throughput by maximizing the batch sizes, decrease of the WIP TAT(Turn Around Time).

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2011.04a
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• pp.97-102
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• 2011

The size of TV and TFT-LCD are bigger and bigger for the next generation exposure equipment install that existing fab are getting a lot of additions. When the new fab build an extension that the shortening of the construction and non-vibration are use cast in place concrete pile method. In this study when lay the foundation of existing fab adjoin use vibration monitoring system are rotator type all casing method among cast in place concrete pile method. The evaluation of ground vibration of rotator type all casing method effect to precision equipment and vibration area of influence.

• Design & Manufacturing
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• v.11 no.2
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• pp.25-28
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• 2017

Semiconductor equipment manufacturers desire to enhance efficiency of Sub Fab to increase semiconductor productivity. For this reason, Sub Fab equipment manufacturers are developing Integrated System that combined modules with multiple facilities. Integrated System is required to apply Mount Leveler of Wedge Type in compliance with weight increase compared with existing single equipment and product shape change. This thesis analyzes main design variables of components of Wedge Mount Leveler and carries out structure analysis using ANSYS, finite element analysis program Analysis shows that main design variables of components of Wedge Mount Leveler has self-locking condition by friction force of Wedge and adjusting bolt. Each friction force hinges upon Wedge angle and Friction Coefficient of contact surface and upon the thread angle and Friction Coefficient of contact surface. Also, as a result of carrying out structure analysis of Wedge Mount Leveler, deflection and stress appears in different depending on the height of the level.

• Journal of the Korean Institute of Gas
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• v.22 no.1
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• pp.78-85
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• 2018

In this study, we analyzed risks of the fabrication process equipment and cleanroom for semiconductor/flat panel display (FPD) manufacturing facilities and studied the fundamental safety measures for the risk factors. We examined the explosion proof design models considering the specificity of equipment and environment, and planned to utilize the findings to provide technical standards and grounds for designing and manufacturing related equipment. We believe that this study will contribute to the establishment of technical standards for semiconductor/FPD industry and businesses in many different ways by providing optimized modeling of high-risk explosion site detection, developing safety standards and hazard countermeasures and voluntary activation of safety certification system for operation of fabrication process equipment.

• Korean Journal of Computational Design and Engineering
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• v.19 no.3
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• pp.214-223
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• 2014

This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.377-378
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• 2008

Morphology is one of important issues when developing a layer of CVD-W. we need to control the process more precisely that is filling gaps between BL(bit line)and DC(direct contact). Whereas we are facing to difficulties like not-filling contacts due to marginal problems in deposition and etching process. This paper is for investigating a method to resolve morphology problem with strengthening the condition of seasoning.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2004.05a
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• pp.195-201
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• 2004

In design stage of high precision manufacture/inspect ion FAB building, it is necessary to investigate the vibration allowable limits of high precision equipment and to study a structure dynamic characteristics of C/R and Sub-structure in order to provide a structure vibration environment to satisfy thess allowable limits. The aim of this study is to investigate the dynamic characteristics of PC-Type mock-up structures designed for next TFT LCD FAB through vibration measurement and analysis procedure, therefore, to provide a proper dynamic structure design for high precision manufacture/inspection work process, which satisfy thess allowable limits.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.43 no.2
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• pp.137-145
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• 2020

Various elements of Fabrication (FAB), mass production of existing products, new product development and process improvement evaluation might increase the complexity of production process when products are produced at the same time. As a result, complex production operation makes it difficult to predict production capacity of facilities. In this environment, production forecasting is the basic information used for production plan, preventive maintenance, yield management, and new product development. In this paper, we tried to develop a multiple linear regression analysis model in order to improve the existing production capacity forecasting method, which is to estimate production capacity by using a simple trend analysis during short time periods. Specifically, we defined overall equipment effectiveness of facility as a performance measure to represent production capacity. Then, we considered the production capacities of interrelated facilities in the FAB production process during past several weeks as independent regression variables in order to reflect the impact of facility maintenance cycles and production sequences. By applying variable selection methods and selecting only some significant variables, we developed a multiple linear regression forecasting model. Through a numerical experiment, we showed the superiority of the proposed method by obtaining the mean residual error of 3.98%, and improving the previous one by 7.9%.

• Journal of the Korea Society for Simulation
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• v.21 no.2
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• pp.41-50
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• 2012

In this study we first explain details of the semiconductor manufacturing processes and cluster tools. Then we discuss the problems in current fab layout and cluster tool architecture. As a solution to these problems, we propose the ILE (In-Line EFEM) architecture in which wafer movements are conducted through interconnected EFEMs (Equipment Front End Modules) instead of AMHS (Automated Material Handling System). Then we model the pilot ILE system using discrete event simulation and analyze the cycle time. Finally we compare three different scenarios of equipment layout in the ILE system in terms of cycle time.