• 제어로봇시스템학회:학술대회논문집
• /
• 2002.10a
• /
• pp.120.5-120
• /
• 2002

1. Introduction 2. Property of FPGA 3. Evolvable Hardware (EHW) 4. Genetic Algorithm Processor (GAP) 5. State Machine 6. Conclusion

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.05a
• /
• pp.466-468
• /
• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fired length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.5
• /
• pp.718-723
• /
• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA. Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fixed length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• v.5 no.3
• /
• pp.206-215
• /
• 2005

In this paper, we propose a new design method of Genetic Algorithm Processor(GAP) and Evolvable Hardware(EHW). All sorts of creature evolve its structure or shape in order to adapt itself to environments. Evolutionary Computation based on the process of natural selection not only searches the quasi-optimal solution through the evolution process, but also changes the structure to get best results. On the other hand, Genetic Algorithm(GA) is good fur finding solutions of complex optimization problems. However, it has a major drawback, which is its slow execution speed when is implemented in software of a conventional computer. Parallel processing has been one approach to overcome the speed problem of GA. In a point of view of GA, long bit string length caused the system of GA to spend much time that clear up the problem. Evolvable Hardware refers to the automation of electronic circuit design through artificial evolution, and is currently increased with the interested topic in a research domain and an engineering methodology. The studies of EHW generally use the XC6200 of Xilinx. The structure of XC6200 can configure with gate unit. Each unit has connected up, down, right and left cell. But the products can't use because had sterilized. So this paper uses Vertex-E (XCV2000E). The cell of FPGA is made up of Configuration Logic Block (CLB) and can't reconfigure with gate unit. This paper uses Vertex-E is composed of the component as cell of XC6200 cell in VertexE

• Proceedings of the Korean Information Science Society Conference
• /
• 2001.10b
• /
• pp.13-15
• /
• 2001

진화 하드웨어(Evolvable Hardware: EHW)는 환경에 적응하여 스스로 하드웨어 구성을 변경할 수 있는 하드웨어로서 최근에 많은 관심과 함께 연구가 이뤄지고 있다. 하지만, 하드웨어의 복잡도가 증가할수록 진화를 위해 탐색해야 하는 해공간의 크기가 기하급수적으로 증가하기 때문에 아직까지 복잡한 하드웨어에 대해서는 좋은 활용방안을 찾지 못하고 있다. 이 논문에서는 이런 복잡한 하드웨어를 모듈별로 나눠서 진화시키는 방법을 제시하여 좀더 효율적인 진화의 가능성을 보인다. 기존에 주로 사용되던 회로 진화 디자인과 이를 모듈별로 나눠서 진화하는 방식을 실험을 통해 비교하고, 효과적으로 진화시간을 단축할 수 있음을 보인다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2002.10d
• /
• pp.244-246
• /
• 2002

진화 하드웨어(Evolvable Hardware)는 환경 적응력이 강하고 최적의 상태를 유연하게 유지하는 하드웨어 설계 기법이나 회로가 복잡해질수록 진화가 어려워지는 문제로 인해 활용이 늦어지고 있다. 본 논문에서는 이를 해결하기 위한 많은 연구 중 회로 진화 과정 분석을 위한 방법으로 개미집단 시스템을 제안한다. 경로 최적화 알고리즘인 개미집단 시스템을 적절히 변형하여 진화 하드웨어에 적용시키는 방법을 제안하고 이를 실험으로 확인하였으며, 실험 결과 하드웨어의 진화 과정을 관찰할 수 있었고, 목표 하드웨어의 해공간 특성이 페로몬으로 분포하고 있음도 관찰할 수 있었다.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.10 no.4
• /
• pp.379-389
• /
• 2000

A cellular automaton is well-known for self-organizing and dynamic behavions in the filed of artifial life. This paper addresses a new neuronic architecture called an evolvable celluar classifier which evolves with the genetic rules (chromosomes) in the non-uniform cellular automata. An evolvable cellular classifier is primarily based on cellular programming, but its mechanism is simpler becaise it utilizes only mutations for the main genetic operators and resmbles the Hopfield network. Therefore, the desirable bit-patterns could be obtained through evolutionary processes for just one individual agent, As a rusult, an evolvable hardware is derived which is applicable to clessification of bit-string information.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 2000.05a
• /
• pp.236-240
• /
• 2000

A cellular automaton is well-known for self-organizing and dynamic behaviors in the field of artificial life. This paper addresses a new neuronic architecture called an evolvable cellular classifier which evolves with the genetic rules (chromosomes) in the non-uniform cellular automata. An evolvable cellular classifier is primarily based on cellular programing, but its mechanism is simpler because it utilizes only mutations for the main genetic operators and resembles the Hopfield network. Therefore, the desirable hi t-patterns could be obtained through evolutionary processes for just one individual agent. As a result, an evolvable hardware is derived which is applicable to classification of bit-string information.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.7
• /
• pp.1553-1557
• /
• 2004

A real-time processing system for embedded hardware genetic algorithm is suggested. In order to operate basic module of genetic algorithm in parallel, such as selection, crossover, mutation and evaluation, dual processors based architecture is implemented. The system consists of two Xscale processors and two FPGA with evolvable hardware, which enables to process genetic algorithm efficiently by distributing the computational load of hardware genetic algorithm to each processors equally. The hardware genetic algorithm runs on Linux OS and the resulted chromosome is executed on evolvable hardware in FPGA. Furthermore, the suggested architecture can be extended easily for a couple of connected processors in serial, making it accelerate to compute a real-time hardware genetic algorithm. To investigate the effect of proposed approach, performance comparisons is experimented for an typical computation of genetic algorithm.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.12 no.5
• /
• pp.462-466
• /
• 2002

Genetic Algorithm (GA) which imitates the process of nature evolution is applied to various fields because it is simple to theory and easy to application. Recently applying GA to hardware, it is to proceed the research of Evolvable Hardware(EHW) developing the structure of hardware and reconstructing it. And it is growing a necessity of GAP that embodies the computation of GA to the hardware. Evolving by GA don't act in the software but in the hardware(GAP) will be necessary for the design of independent EHW. This paper shows the design GAP for fast reconfiguration of EHW.