• Title/Summary/Keyword: Evaporation Coating

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Fabrication, Structure and Gas Sensing Properties of Pt-functionalized ZnS Nanowires

  • Kim, Soohyun;Park, Sunghoon;Jung, Jihwan;Lee, Chongmu
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.315.2-315.2
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    • 2014
  • Pt-functionalized ZnS nanowires were synthesized on Au-deposited c-plane sapphire substrates by thermal evaporation of ZnS powders followed by wet Pt coating and annealing. The $NO_2$ gas sensing properties of multiple-networked Pt-functionalized ZnS nanowire sensors were examined. Scanning electron microscopy showed the nanowires with diameters of 20-80 nm. Transmission electron microscopy and X-ray diffraction showed that the nanowires were wurtzite-structured ZnS single crystals. The Pt-functionalized ZnS nanowire sensors showed enhanced sensing performance to $NO_2$ gas at $150^{\circ}C$ compared to pristine ZnS nanowire sensors. Pristine and Pt-functionalized ZnS nanowire sensors showed responses of 140-211% and 207-488%, respectively, to 1-5 ppm $NO_2$, which are better than or comparable to those of many oxide semiconductor sensors. In addition, the underlying mechanism of the enhancement of the sensing properties of ZnS nanowires by Pt functionalization is discussed.

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Study on the Organic Gate Insulators Using VDP Method (VDP(Vapor Deposition Polymerization) 방법을 이용한 유기 게이트 절연막의 대한 연구)

  • Pyo, Sang-Woo;Shim, Jae-Hoon;Kim, Jung-Soo;Kim, Young-Kwan
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07a
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    • pp.185-190
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    • 2003
  • In this paper, it was demonstrated that the organic thin film transistors were fabricated by the organic gate insulators with vapor deposition polymerization (VDP) processing. In order to form polyimide as a gate insulator, vapor deposition polymerization process was also introduced instead of spin-coating process, where polyimide film was co-deposited by high-vacuum thermal evaporation from 4,4'-oxydiphthalic anhydride (ODPA) and 4,4'-oxydianiline (ODA) and 2,2-bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride (6FDA) and ODA, and cured at $150^{\circ}C$ for 1hr. Electrical output characteristics in our organic thin film transistors using the staggered-inverted top-contact structure obtained to the saturated slop in the saturation region and the subthreshold non-linearity in the triode region. Field effect mobility, threshold voltage, and on-off current ratio in $0.45\;{\mu}m$ thick gate dielectric layer were about $0.17\;cm^2/Vs$, -7 V, and $10^6\;A/A$, respectively. Details on the explanation of compared to organic thin-film transistors (OTFTS) electrical characteristics of ODPA-ODA and 6FDA-ODA as gate insulators by fabricated thermal co-deposition method.

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ELECTRICAL CHARACTERISTICS OF PENTACENE THIN FILM TRANSISTORS WITH STACKED AND SURFACE-TREATED GATE INSULATORS (러빙 처리된 표면의 적층 절연막을 가지는 Pentacene TFT의 전기적 특성)

  • Kang, Chang-Heon;Lee, Jong-Hyuk;Park, Jae-Hoon;Choi, Jong-Sun
    • Proceedings of the KIEE Conference
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    • 2002.07c
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    • pp.1546-1548
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    • 2002
  • In this paper, the electrical characteristics of pentacene thin film transistors(TFTs) with stacked and surface-treated gate insulators have been investigated. The semiconductor layer of pentacene was thermally evaporated onto the stacked gate insulators. For the gate insulating materials. PVP(PolyvinylPhenol) and polystyrene were spin-coated with two different stacking orders, PVP-polystyrene and polystyrene-PVP. Rapid solvent evaporation during the spin-coating processes of these insulating layers produces non-equilibrium phase morphologies accompanied by surface undulations on gate insulator interfaces. This non-equilibrium phase morphology affects the growth mode of the subsequent pentacene layer. Therefore, in order to smoothen the gate dielectric surfaces, gate dielectric surfaces were rubbed laterally along the direction from the drain to the source TFTs with with stacked and surface-treated gate insulators have provided improved operational characteristics.

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Fabrication of Organic Thin Films by Pulsed Laser Deposition (펄스 레이저 증착법을 이용한 유기 박막의 제작)

  • Park, Sang-Moo;Lee, Boong-Joo
    • Journal of the Korean Vacuum Society
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    • v.17 no.5
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    • pp.455-460
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    • 2008
  • In recent years, there has been highly interestedin pulsed laser deposition (PLD) method for fabrication of the organic thin films, as an alternative to conventional fabrication method such as vacuum evaporation and spin coating techniques. In this study, organic thin films of $Alq_3$ (aluminato-tris-8-hydroxyquinolate) and TPD for organic light emitting diodes (OLED) were deposited by PLD using KrF excimer ($\lambda$=278 nm) laser in nitrogen atmosphere. Deposited films were evaluated by photoluminescence(PL), Fourier-transform Infrared Spectroscopy (FT-IR) to study the effect of the laser and $N_2$ atmosphere parameters on the structural and optical properties.

MeV 전자빔 조사를 통한 Pt/Graphene 복합 나노구조의 형성

  • Cha, Myeong-Jun;Song, U-Seok;Kim, Yu-Seok;Jeong, Dae-Seong;Kim, Seong-Hwan;Lee, Su-Il;Park, Jong-Yun
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.570-570
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    • 2012
  • 그래핀(graphene)은 육각형의 탄소원자 한층으로 이루어진 이차원 구조체로써 우수한 물리적, 전기적 특성으로 인해 다양한 분야에서 응요을 위한 연구가 활발히 진행되고 있다. 특히, 그래핀과 금속 나노입자의 복합구조는 수소 저장체, 가스센서, 연료전지, 화학 촉매등의 다양한 분야에서 응용이 가능하다. 현재까지 그래핀/금속나노입자 복합구조의 제작 방법에는 열증발(thermal evaporation), 전기도금법(electrodeposition), 표면 기능화(surface functionalization)를 이용한 방법이 보고되었다. 하지만 이러한 방법은 긴 공정시간이 요구되며, 나노입자의 크기 분포가 넓다는 단점을 지닌다. 본 연구에서는 화학기상증착법을 통해 합성된 그래핀이 전사된 SiO2 (300nm)/Si 기판에 염화기가 포함된 백금 화합물 분산용액을 스핀코팅(spin-coating)하고 MeV 전자빔을 조사하여 Pt/grapheme 복합구조를 형성하였다. 이 방법은 균일한 크기 분포의 나노입자의 형성이 가능하며, 간단하고, 대면적 공정이 가능하며, 다른 방법에 비해 그래핀의 결함형성이 적다는 장점을 지닌다. Pt/grapheme 의 기하학적 구조를 주사전자현미경(scanning electron microscopy)와 투과전자현미경(transimission)을 통해 분석하였고, Pt와 graphene의 일함수(workfunction)의 차이에 의해 야기되는 전하이동에 의한 도핑(doping)현상을 라만 분광기(Raman spectroscopy)와 X-선 광전자 분광기(X-ray photoelectron spectroscopy)를 통해 분석하였다.

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Highly Sensitive and Selective Gas Sensors Using Catalyst-Loaded SnO2 Nanowires

  • Hwang, In-Sung;Lee, Jong-Heun
    • Journal of Sensor Science and Technology
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    • v.21 no.3
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    • pp.167-171
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    • 2012
  • Ag- and Pd-loaded $SnO_2$ nanowire network sensors were prepared by the growth of $SnO_2$ nanowires via thermal evaporation, the coating of slurry containing $SnO_2$ nanowires, and dropping of a droplet containing Ag or Pd nanoparticles, and subsequent heat treatment. All the pristine, Pd-loaded and Ag-loaded $SnO_2$ nanowire networks showed the selective detection of $C_2H_5OH$ with low cross-responses to CO, $H_2$, $C_3H_8$, and $NH_3$. However, the relative gas responses and gas selectivity depended closely on the catalyst loading. The loading of Pd enhanced the responses($R_a/R_g$: $R_a$: resistance in air, $R_g$: resistance in gas) to CO and $H_2$ significantly, while it slightly deteriorated the response to $C_2H_5OH$. In contrast, a 3.1-fold enhancement was observed in the response to 100 ppm $C_2H_5OH$ by loading of Ag onto $SnO_2$ nanowire networks. The role of Ag catalysts in the highly sensitive and selective detection of $C_2H_5OH$ is discussed.

Conformal $Al_{2}O_{3}$ nano-coating of ZnO nanowires (ZnO 나노와이어에 ALD 방법으로 균일하게 코팅된 $Al_{2}O_{3}$)

  • Hwang, Joo-Won;Min, Byung-Don;Lee, Jong-Su;Keem, Ki-Hyun;Kang, Myung-Il;Kim, Sang-Sig
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.11a
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    • pp.47-50
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    • 2002
  • ZnO nanowires were coated conformally with aluminum oxide ($Al_{2}O_{3}$) material by atomic layer deposition (ALD). The ZnO nanowires were first synthesized on a Si (100) substrate at $1380^{\circ}C$ from ball-milled ZnO powders by a thermal evaporation procedure with an argon carrier gas without any catalysts; the length and diameter of these ZnO nanowires are $20\sim30{\mu}m$ and $50{\sim}200$ nm, respectively. $Al_{2}O_{3}$ films were then deposited on these ZnO nanowires by ALD at a substrate temperature of $300^{\circ}C$ using trimethylaluminum (TMA) and distilled water ($H_{2}O$). Transmission electron microscopy (TEM) images of the deposited ZnO nanowires revealed that 40nm-thick $Al_{2}O_{3}$ cylindrical shells surround the ZnO nanowires.

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Characteristics of Laser Wafer Dicing (레이저를 이용한 웨이퍼 다이싱 특성)

  • Lee, Young-Hyun;Choi, Kyung-Jin;Yoo, Seung-Ryeol
    • Journal of the Semiconductor & Display Technology
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    • v.5 no.3 s.16
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    • pp.5-10
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    • 2006
  • This paper investigates cutting qualities after laser dicing and predicts the problems that can be generated by laser dicing. And through 3 point bending test, die strength is measured and the die strength after laser dicing is compared with the die strength after mechanical sawing. Laser dicing is chiefly considered as an alternative to overcome the defects of mechanical sawing such as chipping on the surface and crack on the back side. Laser micromachining is based on the thermal ablation and evaporation mechanism. As a result of laser dicing experiments, debris on the surface of wafer is observed. To eliminate the debris and protect the surface, an experiment is done using a water soluble coating material and ultrasonic. The consequence is that most of debris is removed. But there are some residues around the cutting line. Unlike mechanical sawing, chipping on the surface and crack on the back side is not observed. The cross section of cutting line by laser dicing is rough as compared with that by mechanical sawing. But micro crack can not be seen. Micro crack reduces die strength. To measure this, 3 point bending test is done. The die strength after laser dicing decreases to a half of the die strength after mechanical sawing. This means that die cracking during package assembly can occur.

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Dielectric Properties of PZT(20/80)/PZT(80/20) Heterolayered Thick Films Fabricated by Screen-printing Method

  • Lee, Sung-Gap;Lee, Young-Hie
    • Transactions on Electrical and Electronic Materials
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    • v.7 no.3
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    • pp.129-133
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    • 2006
  • Ferroelectric PZT heterolayered thick films were fabricated by the alkoxide-based sol-gel method. PZT(20/80) and PZT(80/20) paste were made and alternately screen-printed on the alumina substrates. The coating and drying procedure was repeated 4 times to form the heterolayered thick films. The thickness of the PZT heterolayered thick films was approximately $60{\mu}m$. All PZT thick films showed the typical XRD patterns of a polycrystalline rhombohedral structure. And in the PZT thick films sintered at $1100^{\circ}C$, the pyrochlore phase was observed due to the evaporation of PbO. The relative dielectric constant and the dielectric loss of the PZT thick films sintered at $1050^{\circ}C$ were 445.2 and 1.90 % at 1 kHz, respectively. The remanent polarization and coercive field of the PZT thick films sintered at $1050^{\circ}C$ were $14.15{\mu}C/cm^2$ and 19.13 kV/cm, respectively.

Stability of Organic Thin-Film Transistors Fabricated by Inserting a Polymeric Film (고분자막을 점착층으로 사용한 유기 박막 트랜지스터의 안정성)

  • Hyung, Gun-Woo;Pyo, Sang-Woo;Kim, Jun-Ho;Kim, Young-Kwan
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.61-62
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    • 2006
  • In this paper, it was demonstrated that organic thin- film transistors (OTFTs) were fabricated with the organic adhesion layer between an organic semiconductor and a gate insulator by vapor deposition polymerization (VDP) processing. In order to form polymeric film as an adhesion layer, VDP process was also introduced instead of spin-coating process, where polymeric film was co-deposited by high-vacuum thermal evaporation from 6FDA and ODA followed by curing. The saturated slop in the saturation region and the subthreshold nonlinearity in the triode region were c1early observed in the electrical output characteristics in our organic thin film transistors using the staggered-inverted top-contact structure. Field effect mobility, threshold voltage, and on-off current ratio in 15-nm-thick organic adhesion layer were about $0.5\;cm^2/Vs$, -1 V, and $10^6$, respectively. We also demonstrated that threshold voltage depends strongly on the delay time when a gate voltage has been applied to bias stress.

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