• Journal of Advanced Marine Engineering and Technology
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• v.21 no.1
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• pp.59-65
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• 1997

In this paper, a feedforward amplifier with error correction is designed and implemented. This amplifier is composed of operational amplifier, the performance of which is compared with that of the reference amplifier without feedforward error correction. As a result, the sec¬ondary harmonics level is improved about 10 [dB]. Therefore it is shown that the proposed feedforward amplifier network is to be adopted able for wide - band amplifiers.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.185-188
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• 2001

This paper proposes an error amplifier circuit using OTA(Operational Transconductance Amplifier) which is the main constituent element in pulse width modulation circuit. The proposed OTA error amplifier circuit is featured by simple circuit configuration, excellent high frequency characteristics and bias current controlled output. Through the experiment of pulse width modulation circuit, the validity of the operation of the OTA error amplifier circuit is verified.

• Journal of IKEEE
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• v.14 no.2
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• pp.90-97
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• 2010

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device and DTMOS Error Amplifier is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS(DT-CMOS) with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an DT-CMOS error amplifier and a comparator circuit as a block. the proposed DT-CMOS Error Amplifier has 72dB DC gain and 83.5deg phase margin. also Error Amplifier that use DTMOS more than CMOS showed power consumption decrease of about 30%. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device is achieved the high efficiency near 96% at 100mA output current. And DC-DC converter is designed with Low Drop Out regulator(LDO regulator) in stand-by mode which fewer than 1mA for high efficiency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.762-768
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• 2003

This paper reports the effects of gain flatness for linearity improvement of feedforward power amplifier fur IMT-2000 band. To investigate the operational characteristics for gain flatness of each amplifier, WCDMA 4FA input signal was used and measured 10 W output power. Especially, linearity improvement for variation of gain flatness of each amplifier was investigated that have an effect on linearity improvement such as delay line, phase, and amplitude imbalances. Variation of gain flatness of main amplifier is 40 MHz and of error amplifier is 40 MHz and 80 MHz bandwidth, respectively. Measured results, gain flatness of main amplifier is less than 1.5 dB and of error amplifier is less than 0.5 dB for more than 20 dB improvement at 5 MHz offset. In addition to that results, the characteristics of feedforward amplifier are drastically varied by gain flatness of error amplifier and it is shown that gain flatness of error amplifier is more important factor for linearity improvement.

• Journal of Navigation and Port Research
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• v.27 no.2
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• pp.209-215
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• 2003

In this paper. We tested and fabricated the error amplifier for the 15 Watt linear power amplifier for the IMT-2000 baseband station. The error amplifier was comprised of subtractor for detecting intermodulation distortion, variable attenuator for control amplitude, variable phase shifter for control phase, low power amplifier and high power amplifier. This component was designed on the RO4350 substrate and integrated the aluminum case with active biasing circuit. For suppression of spurious, the through capacitance was used. The characteristics of error amplifier measured up to 45 dB gain, $\pm$0.66 dB gain flatness and -15 dB input return loss. Results of application to the 15 Watt feedforward Linear Power Amplifier, the error amplifier improved with 27 dB cancellation from 34 dBc to 61 dBc IM$_3$.

• Journal of the Korean Institute of Navigation
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• v.20 no.3
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• pp.117-126
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• 1996

Generally, the distortion of the negative feedback amplifier is reduced by a factor equal to the return difference (1+${\beta}_1A_1$), but the proposed feedforward amplifier is reduced by a factor equal to the square of the return difference (1+${\beta}_1A_1$). In this paper, a feedforward amplifier with error correction is designed and implemented. So as to evaluate the characteristics of the harmonic distortion that the inverting feedforward amplifier is compared with that of the reference amplifier without feedforward error correction. It is confirmed that the proposed method should be able to reduce much greater than compared with a conventional negative feedback amplifier. Therefore it should be noted that the proposed feedforward amplifier network is also acceptable for wide-band amplifiers and the network which is demanded to improve the harmonic distortion.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1407-1413
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• 2000

This paper presents a feedforward linear power amplifier (LPA) using error feedback technique to achieve low intermodulation distortions(IMD) of power amplifiers for base stations. Especially, the proposed linear power amplifier is applied to feedforward technique combined with error feedback technique, which has no loss of amplifier gain unlike typical feedback technique. The proposed LPA is designed by using HP ADS ver. 1.3, fabricated. When two-tone signals at 1850 MHz and 1851.25 MHz with -7 dBm/tone from synthesizers are injected into the main power amplifier with gain of 28 dB and P1dB of 1W, the proposed LPA could reduce more than 35 dB.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.211-212
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• 2006

This paper represents a Doherty amplifier with analog predistorter to improve the linearity of the Doherty amplifier while preserving the high efficiency. A $3^{rd}$-order predistorter cancels $5^{th}$-order intermodulation (IM5) as well as $3^{rd}$-order intermodulation (IM3) components by their same phase difference in the predistorter and Doherty amplifier. This is accomplished by independently controlling their phase by using the phase-controlled error generator in the predistorter. For experimental verification, a $3^{rd}$-order predistorter has been implemented and tested in a 180-W Doherty amplifier at the wide-band code division multiple access (WCDMA) band. The measured results show good performance with the predistortion Doherty amplifier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.1
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• pp.116-123
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• 2000

This paper presents a linearizer using the feedforward loop which can be applied to PCS base-station applications. This linearizer used a IM amplifier and an auxiliary amplifier in order to remove delay lines used in the predistortor using the feedforward technique. The delay line in error loop is changed by the main power amplifier(PA) and the error amplifier is utilized to amplify the error signal which fed to the output of main amplifier. The linearizer was simulated by HP ADS ver 1.1 and fabricated on GML 1000 with thickness of 0.8 mm and dielectric constant of 3.2. Two-tone signals at 1.85 GHz and 1.851 GHz with -7dBm/tone from synthesizers are injected into the main PA. The main PA with a 27 dB gain and a $P_{1dB}$ of 29 dBm(two-tone) was utilized. The reduction of intermodulation distortion (IMD) is around 17 dB.