• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1075-1081
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• 2011

In this paper, we proposed the DS-SS modem-based communication system for long distance wireless-transmission. The module we designed in this approach contained both convolution encoder and gold-code generator, which aimed at error correcting, T-DES encryption algorithm and spread-spectrum as well. It embodied PC-based GUI program in order to control the such command signal as data transceiver. This program also used to control the specific FPGA/MCU which is able to verify and interface to the modem. We demonstrated the communication system to verify its proper operation by using GUI program and designed hardware. A set of experiments are conducted and as a result, proposed communication system is well operated as the design specification.

• Journal of Korea Multimedia Society
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• v.7 no.1
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• pp.73-79
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• 2004

In this paper, we propose an efficient soft decision decoding algorithm for linear block codes. A conventional soft decision decoder have to invoke a hard decision decoder several times to estimate its soft decision values. However, in this method, we may not have candidate codewords, thus it is very difficult to produce soft decision values. We solve this problem by introducing an efficient algorithm to search candidate codewords. By using this, we can highly reduce the cases we cannot find candidate codewords. We estimate the performance of the proposed algorithm by using the computer simulations. The simulation is performed for binary (63, 36) BCH code in fading channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.8
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• pp.1839-1844
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• 2015

The low-density parity-check(LDPC) code has been adopted in many communication standards due to its error correcting performance, and the quasi-cyclic LDPC(QC-LDPC) is widely used because of implementation easiness. In the QC-LDPC decoder, a cyclic-shifter is required to rotate data in various sizes. This kind of cyclic-shifters are called multi-size circular shifter(MSCS), and this paper proposes a low-complexity structure for MSCS. In the conventional serially-placed two barrel-rotators, the unnecessary multiplexers are revealed and removed, leading to low-complexity. The experimental results show that the area is reduced by about 12%.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.10
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• pp.1783-1798
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• 2011

Recently, a cryptographic construct, called fuzzy vault, has been proposed for crypto-biometric systems, and some implementations for fingerprint have been reported to protect the stored fingerprint template by hiding the fingerprint features. In this paper, we implement the fuzzy fingerprint vault, combining fingerprint verification and fuzzy vault scheme to protect fingerprint templates. To implement the fuzzy fingerprint vault as a complete system, we have to consider several practical issues such as automatic fingerprint alignment, verification accuracy, execution time, error correcting code, etc. In addition, to protect the fuzzy fingerprint vault from the correlation attack, we propose an approach to insert chaffs in a structured way such that distinguishing the fingerprint minutiae and the chaff points obtained from two applications is computationally hard. Based on the experimental results, we confirm that the proposed approach provides higher security than inserting chaffs randomly without a significant degradation of the verification accuracy, and our implementation can be used for real applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.801-809
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• 2007

LDPC Low Density Parity Check) code, which is an error correcting code determined to be applied to the 4th generation mobile communication systems, requires a heavy computational complexity due to iterative decodings to achieve a high BER performance. This paper proposes an algorithm to reduce the number of decoding iterations to increase performance of the decoder in decoding latency and power consumption. Measuring changes between the current decoded LLR values and previous ones, the proposed algorithm predicts directions of the value changes. Based on the prediction, the algorithm inverts the sign bits of the LLR values to speed up convergence, which means parity check equation is satisfied. Simulation results show that the number of iterations has been reduced by about 33% without BER performance degradation in the proposed decoder, and the power consumption has also been decreased in proportional to the amount of the reduced decoding iterations.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.29 no.2
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• pp.201-208
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• 2011

With the increase in the number of smartphone users, precise 3D positional information is required by various applications. The positioning accuracy using civilian single-frequency pseudoranges is at the level of 10 m or so, but most applications these days are asking for a sub-meter level Therefore, instead of an absolute positioning technique, the VRS-based differential approach is applied along with the correction of the double-differenced (DD) residual errors using FKP (Flachen-Korrektur-Parameter). The VRS (Virual Reference Station) is located close to the rover, and the measurements are generated by correcting the geometrical distance to those of the master reference station. Since the unmodeled errors are generally proportional to the length of the baselines, the correction parameters are estimated by fitting a plane to the DD pseudorange errors of the CORS network. The DD positioning accuracy using 24 hours of C/A code measurements provides the RMS errors of 37 cm, 28 cm for latitudinal and longitudinal direction, respectively, and 76 cm for height. The accuracy of the horizontal components is within ${\pm}0.5m$ for about 90% of total epochs, and in particular the biases are significantly decreased to the level of 2-3 cm due to the network-based error modeling. Consequently, it is possible to consistently achieve a sub-meter level accuracy from the single-frequency pseudoranges using the VRS and double-differenced error modeling.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.939-947
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• 2010

The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1010-1019
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• 2004

In this paper, we represent Nakagami-m fading channel as finite-State Markov Channel (FSMC) and analyze the performance of wireless communication system with varying the fading channel condition. In FSMC model, the received signal's SNR is divided into finite intervals and these intervals are formed into Markov chain states. Each state is modeled by a BSC and the transition probability is dependent upon the physical characterization of the channel. The steady state probability and average symbol error rate of each state and transition probability are derived by numerical analysis and FSMC model is formed with these values. We found that various fading channels can be represented with FSMC by changing state transition index. In fast fading environment in which state transition index is large, the channel can be viewed as i.i.d. channel and on the contrary, in slow fading channel where state transition index is small, the channel can be represented by simple FSMC model in which transitions occur between just adjacent states. And we applied the proposed FSMC model to analyze the coding gain of random error correcting code on various fading channels via computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.97-103
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• 2004

In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.3 s.309
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• pp.76-81
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• 2006

Recently, Finite field is applied the cryptography in the modern multimedia communication. Especially, block codes such as Elliptic Curve Cryptosystem and Reed-Solomon code among the error correcting codes are defined with finite field. Also, finite field algorithm is conducting the research actively because many kind of application parts need the real time operating ability therefore the exclusive hardware have been implementing. In this paper, we proposed the inverse finite field algorithm over GF($2^8$) using finite composite field and implemented in a hardware, and then compare this hardware with the currently used 'Itoh and Tsujii' hardware in respect to structure, area and computation time. Furthermore, this hardware was inserted into the AES SubBytes block and implemented on FPGA emulator board to confirm that the superiority of the proposed algorithm through the performance evaluation.