• 대한전자공학회논문지
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• 제23권1호
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• pp.65-73
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• 1986

Experiment have been conducted about thin oxide characteristics according to O2/N2 ratio needed for EEPROM cell fabrication. As a result, we think that there is no problem even if we grow oxide layer with large O2/N2 ratio and short exidation time and when the water is implated by As before oxidation, the oxide breakdown field is about IMV/cm lower than that is not implanted. Especially, the thin oxide characteristic seems to be affected largely by wafer cleaning and oxidation in air. On the basis of these, tunnel type EEPROM cell is fabricated by 3um CMOS process and its characteristic is studied. Tunnel oxide thickness(100\ulcorner is chosen to allow Fowler-Nordheim tunneling to charge the floating gate at the desired programming voltage and tunnel area(2x2um\ulcorneris chosen to increase capacitive coupling ratio. For program operation, high voltage (20-22V) is applied to the control gate, while both drain and source are gdrounded. The drain voltage for erase is 16V. It is shown that charge retention characteristics is not limited by leakage in the oxide and program/erase endurance is over 10E4 cycles of program erase operation.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 1991년도 춘계연구발표회 논문개요집
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• pp.75-76
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• 1991

• 정보처리학회지
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• 제23권4호
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• pp.4-9
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• 2016

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2002년도 학술대회논문집
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• pp.29-33
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• 2002

Period which does an electric condition of panel in reset in the driving method of PDP is reset period. This research experimentally analyzed the priming discharge characteristic of reset period. The amount of wall charge and the accumulation time accumulated by priming discharge are unrelated to width of priming pulse. And, self-erase discharge has the relation in the amount of wall charge by priming discharge. Then, it relates also to space charge generated by priming discharge. Moreover, space charge which helps self-erase discharge exists to about 22$mutextrm{s}$ after generating priming discharge. And, it is suitable within 12$mutextrm{s}$ of priming pulse width for efficient reset.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1991년도 추계학술대회 논문집
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• pp.48-51
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• 1991

Short channel Nonvolatile EEPROM memory devices were fabricated to CMOS 1M bit design rule, and reviews the characteristics and applications of SNOSFET. Application of SNOS field effect transistors have been proposed for both logic circuits and nonvolatile memory arrays, and operating characteristics with write and erase were investigated. As a results, memory window size of four terminal devices and two terminal devices was established low conductance stage and high conductance state, which was operated in “1” state and “0”state with write and erase respectively. And the operating characteristics of unit cell in matrix array were investigated with implementing the composition method of four and two terminal nonvolatile memory cells. It was shown that four terminal 2${\times}$2 matrix array was operated bipolar, and two termineal 2${\times}$2 matrix array was operated unipolar.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.152-154
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• 2005

This paper proposes the new subfield method to erase reverse gray levels and low gray level contour in AC plasma display panel(PDP). In the conventional method, it is supposed that output luminance levels of a PDP increase regularly. But actual output luminance levels of a PDP increase irregularly. Therefore, conventional methods are unable to effectively reduce low gray-level contours and reverse gray levels. Accordingly, a new subfield method is applied to improve the low gray-level expression in PDP. Conclusively this paper clear proof that a new subfield method can suppress low gray-level contours and reverse gray levels more effectively than conventional methods.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.425-428
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• 1998

In this work, single-poly EEPROM has been designed and fabricated by using standard 0.8.mu.m CMOS process. The initial threshold voltage was aobut 0.8V but it increased ot about 6.5V after programming at Vds=11.5V and Vcg=6.5V. After erasing devices at Vs=14.2V, the threshold voltage decreased to about 1.5V. The programming time and erasing trime wree about 6ms. and 100ms. respectively. The erasing time can be reduced by applying a series of shorter erase pulse s instead of a long single erase pulse.

• 한국전기전자재료학회논문지
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• 제17권10호
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• pp.1125-1131
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• 2004

Misfiring is usually observed at high ambient temperature in plasma display panel (PDP). This leads to bad image quality and limits the productivity of PDP industry. In this paper, experimental observations and improvement on the misfiring at high ambient temperature have been studied. In order to reduce the high ambient temperature misfiring different slope of ramp erase pulse corresponding to the temperature are applied. The experimental results show that the suggested method is quite effective for reducing the high temperature misfiring phenomena.

• 한국전기전자재료학회논문지
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• 제19권11호
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• pp.994-999
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• 2006

For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.

• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.