• Journal of Power Electronics
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• v.13 no.4
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• pp.626-635
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• 2013

An analysis of the junction capacitance in resonant rectifiers which has a significant impact on the operating point of resonance circuits is studied in this paper, where the junction capacitance of the rectifier diode is to decrease the resonant current and output voltage in the circuit when compared with that in an ideal rectifier diode. This can be represented by a simplified series resonant equivalent circuit and a voltage transfer function versus the normalized operating frequency at varied values of the resonant capacitor. A low voltage to high voltage push-pull DC/DC resonant converter was used as a design example. The design procedure is based on the principle of the half bridge class-DE resonant rectifier, which ensures more accurate results. The proposed scheme provides a more systematic and feasible solution than the conventional resonant push-pull DC/DC converter analysis methodology. To increase circuit efficiency, the main switches and the rectifier diodes can be operated under the zero-voltage and zero-current switching conditions, respectively. In order to achieve this objective, the parameters of the DC/DC converter need to be designed properly. The details of the analysis and design of this DC/DC converter's components are described. A prototype was constructed with a 62-88 kHz variable switching frequency, a 12 $V_{DC}$ input voltage, a 380 $V_{DC}$ output voltage, and a rated output power of 150 W. The validity of this approach was confirmed by simulation and experimental results.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1298-1307
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• 2017

The constant on-time current-mode controlled (COT-CMC) switching dc-dc converter is stable, with no subharmonic oscillation in its current loop when a voltage ripple in its outer voltage loop is ignored. However, when its output capacitance is small or its feedback gain is high, subharmonic oscillation may occur in a COT-CMC buck converter with a proportional-integral (PI) compensator. To investigate the subharmonic instability of COT-CMC buck converters with a PI compensator, an accurate reduced-order asynchronous-switching map model of a COT-CMC buck converter with a PI compensator is established. Based on this, the instability behaviors caused by output capacitance and feedback gain are investigated. Furthermore, an approximate instability condition is obtained and design-oriented stability boundaries in different circuit parameter spaces are yielded. The analysis results show that the instability of COT-CMC buck converters with a PI compensator is mainly affected by the output capacitance, output capacitor equivalent series resistance (ESR), feedback gain, current-sensing gain and constant on-time. The study results of this paper are helpful for the circuit parameter design of COT-CMC switching dc-dc converters. Experimental results are provided to verify the analysis results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.6
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• pp.946-951
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• 2000

In this paper, we showed the characteristic of transmission line with DCS (Defected Ground Structure), which is etched on the metallic ground plane. And we extracted the equivalent element value of DGS section. Effects of a lumped element placed on DGS section were investigated by employing DGS of dumbbell shape and parallel resonator with DGS. Chip type resistor, inductor, and capacitor were chosen as lumped elements for experiments. Experimental results show that the Q-factor and resonant frequency of the proposed DGS section can be controlled directly by using the external lumped element.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.808-812
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• 2006

In this dissertation, Ru-Zr metal gate electrode deposited on two kinds of dielectric were formed for MOS capacitor. Sample co-sputtering method was used as a alloy deposition method. Various atomic composition was achieved when metal film was deposited by controlling sputtering power. To study the characteristics of metal gate electrode, C-V(capacitance-voltage) and I-V(current-voltage) measurements were performed. Work function and equivalent oxide thickness were extracted from C-V curves by using NCSU(North Carolina State University) quantum model. After the annealing at various temperature, thermal/chemical stability was verified by measuring the variation of effective oxide thickness and work function. This dissertation verified that Ru-Zr gate electrodes deposited on $SiO_{2}\;and\;ZrO_{2}$ have compatible work functions for NMOS at the specified atomic composition and this metal alloys are thermally stable. Ru-Zr metal gate electrode deposited on $SiO_{2}\;and\;ZrO_{2}$ exhibit low sheet resistance and this values were varied with temperature. Metal alloy deposited on two kinds of dielectric proposed in this dissertation will be used in company with high-k dielectric replacing polysilicon and will lead improvement of CMOS properties.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1110-1121
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• 2016

The mathematical model of a three phase PWM converter under the stationary αβ reference frame is deduced and constructed based on a Proportional-Resonant (PR) regulator, which can replace trigonometric function calculation, Park transformation, real-time detection of a Phase Locked Loop and feed-forward decoupling with the proposed accurate calculation of the inductance voltage vector. To avoid the parallel resonance of the LCL topology, the active damping method of the proportional capacitor-current feedback is employed. As to current vector error elimination, an optimized PR controller of the inner current loop is proposed with the zero-pole matching (ZPM) and cancellation method to configure the regulator. The impacts on system's characteristics and stability margin caused by the PR controller and control parameter variations in the inner-current loop are analyzed, and the correlations among active damping feedback coefficient, sampling and transport delay, and system robustness have been established. An equivalent model of the inner current loop is studied via the pole-zero locus along with the pole placement method and frequency response characteristics. Then, the parameter values of the control system are chosen according to their decisive roles and performance indicators. Finally, simulation and experimental results obtained while adopting the proposed method illustrated its feasibility and effectiveness, and the inner current loop achieved zero static error tracking with a good dynamic response and steady-state performance.

• Journal of Power Electronics
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• v.17 no.4
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• pp.1048-1057
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• 2017

An indirect matrix converter (IMC) is a modern power generation system that enables a direct ac/ac conversion without the need for any bulky and limited lifetime electrolytic capacitor. This system also allows four-quadrant operation, generation of sinusoidal output voltage waveforms with variable frequency and amplitude, and control of input power factor. This study proposes a pulse-width modulation-based sliding-mode controller to achieve unity input-power factor operation of the IMC independently of the active power exchanged with the grid, as well as a fast dynamic response. The designed equivalent control law determines, at each sampling period, the appropriate q-axis component of the modulated input current to be injected into the grid through the LC input filter. An integral term of the error is included in the expression of the sliding surface to increase the accuracy of the control method. A double space vector modulation method is used to synthesize the direction of the space vector of the input currents as required by the sliding-mode controller and the space vectors of the target output voltages. Simulation and experimental results are provided to show the effectiveness and evaluate the performance of the proposed control method.

• Journal of Power Electronics
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• v.17 no.4
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• pp.892-904
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• 2017

A design of a Class-E inverter with only one inductor and one capacitor is presented. It is operated at the optimal operation mode for domestic cooker. The design principle is based on the zero-voltage derivative switching (ZVDS) of the Class-E inverter with a parallel load network, which is a parallel resonant equivalent circuit. An induction load characterization is obtained from a large-signal excitation test bench, which is the key to an accurate design of the induction cooker system. Consequently, the proposed scheme provides a more systematic, simple, accurate, and feasible solution than the conventional quasi-resonant inverter analysis based on series load network methodology. The derivative of the switch voltage is zero at the turn-on transition, and its absolute value is relatively small at the turn-off transition. Switching losses and noise are reduced. The parameters of the ZVDS Class-E inverter for the domestic induction cooker must be selected properly, and details of the design of the components of this Class-E inverter need to be addressed. A 1,200 W prototype is designed and evaluated to verify the validation of the proposed topology.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.857-862
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• 2008

This paper evaluate the performance using a simulated 490KHz narrow band filter based on characteristic parameters appropriately extracted from 490KHz band-pass filter after considering each characteristic, which is modeled on equivalent circuit and applied to NAVTEX receiver using crystal oscillator. The evaluation results show that the value of a series capacitor of crystal oscillator has only little capacity by Cs=21.094fF and the bandwidth characteristics of filter go worse as the capacity value of crystal oscillator grow increase. Moreover, the series inductance value of crystal oscillator has a relatively big value by L=5H, therefore the bandwidth characteristic according as inductance's capacity shows more little effect than the capacity.

• Nuclear Engineering and Technology
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• v.54 no.6
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• pp.2023-2030
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• 2022

A novel pulse fitting analysis (PFA) method is presented for the acquisition of nuclear spectra. The charging process of the feedback capacitor in the resistive feedback charge-sensitive preamplifier is equivalent to the impulsive pulse, and its impulse response function (IRF) can be obtained by non-linear fitting of the falling edge of the nuclear pulse. The integral of the IRF excluding the baseline represents the energy deposition of the particles in the detector. In addition, since the non-linear fitting process in PFA method is difficult to achieve in the conventional architecture of spectroscopy system, a new multi-channel analyzer (MCA) based on Zynq SoC is proposed, which transmits all the data of nuclear pulses from the programmable logic (PL) to the processing system (PS) by high-speed AXI-Stream in order to implement PFA method with precision. The linearity of new MCA has been tested. The spectrum of ¹³⁷Cs was obtained using LaBr₃(Ce) scintillator detector, and was compared with commercial MCA by ORTEC. The results of tests indicate that the MCA based on PFA method has the same performance as the commercial MCA based on pulse height analysis (PHA) method and excellent linearity for γ-rays with different energies, which infers that PFA method is an effective and promising method for the acquisition of spectra. Furthermore, it provides a new solution for nuclear pulse processing algorithms involving regression and iterative processes.