• Journal of Electrical Engineering and Technology
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• 제1권2호
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• pp.233-236
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• 2006

A 3-D numerical simulation of a buried-channel CCD (Charge Coupled Device) with a deep depletion has been performed to investigate its electrical and physical behaviors. Results are presented for a deep depletion CCD (EEV CCD12; JET-X CCD) fabricated on a high-resistivity $(1.5k\Omega-cm)\;65{\mu}m$ thick epi-layer, on a $550{\mu}m$ thick p+ substrate, which is optimized for X-ray detection. Accurate predictions of the Potential minimum and barrier height of a CCD Pixel as a function of mobile electrons are found to give good charge transfer. The depletion depth approximation as a function of gate and substrate bias voltage provided average errors of less than 6%, compared with the results estimated from X-ray detection efficiency measurements. The result obtained from the transient simulation of signal charge movement is also presented based on 3-Dimensional analysis.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1152-1155
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• 1995

An analytic model for the optimum design of the power MOSFET considering the degradation of the breakdown voltage by the three dimensional effect is proposed. The proposed method gives the optimum design parameters such as the lateral radius of window curvature and the doping concentration of the epi-layer, which does not minimize the on-resistance but also maintains the required breakdown voltage. The analytical results are verified by the quasi 3D simulation tools, MEDICI, and it is found that the proposed method may be a good guideline for the design of power MOSFET.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.51-51
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• 2009

In this paper, we proposed GaN trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, GaN and SiC power devices is next generation power semiconductor devices. We carried out modeling of GaN SIT with 2-D device and process simulator. As a result of modeling, we obtained 340V breakdown voltage. The channel thickness was 3um and the channel doping concentration is 1e17cm-3. And we carried out thermal characteristics, too.

• 전자공학회논문지A
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• 제32A권11호
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• pp.79-85
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• 1995

In this paper, an epi layer and a device structure for InP/InGaAs p-i-n/HBT OEIC is designed for a receiving frontend of high speed optical communications. A 3 stage transimpedance circuit using the p-i-n/HBT device is also designed by SPICE simulations for a high sensitivity including ISI noises at a given bit rate. Our simulations show that the Personick's assumption which is not commonly satisfied have estimated a photoreceiver sensitivity too high, so thus we have to also consider ISI noises in OCIC receiver designs.

• 한국전기전자재료학회논문지
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• 제22권12호
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• pp.1018-1022
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• 2009

In this paper, we proposed GaN trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, GaN and SiC power devices is next generation power semiconductor devices. We carried out modeling of GaN SIT with 2-D device and process simulator. As a result of modeling, we obtained 340 V breakdown voltage. The channel thickness was 3 urn and the channel doping concentration is $1e17\;cm^{-3}$. And we carried out thermal characteristics, too.

• 한국전기전자재료학회논문지
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• 제27권9호
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• pp.551-554
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• 2014

This paper was showed latch up characteristics of super junction power MOSFET by parasitic thyristor according to trench etch angle. As a result of research, if trench etch angle of super junction MOSFET is larger, we obtained large latch up voltage. When trench etch angle was $90^{\circ}$, latch up voltage was more 50 V. and we got 700 V breakdown voltage. But we analyzed on resistance. if trench etch angle of super junction MOSFET is larger, we obtained high on resistance. Therefore, we need optimal point by simulation and experiment for solution of trade off.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제37회 하계학술대회 초록집
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• pp.189-189
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• 2009

• 대한전자공학회논문지
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• 제27권5호
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• pp.737-746
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• 1990

Ga0.47In0.53As PIN photodiodes(PD) having various areas have been fabricated by liquid phase epitaxial techniques. Ternary melt has been baked out at 675\ulcorner in H2 atmosphere for 20 hours before growth, which resulted in reduction of background carrier concentration of grown epi-layer. Also, lattice mismatch has been controlled within 0.01%. The room temperature performance of 10**-4cm\ulcornerarea PIN PD at a bias voltage of -5V were` quantum efficiency(with no antireflection coating)=60% for 1.3\ulcorner light source, dark current\ulcorner5nA, and capacitance\ulcornerpE. Frequency response measurement of packaged PIN PD has shown that cut-off frequency (f-3dB) was 961MHz. This PD has shown a good eye pattern when it was incorporated in a 565Mbps optical receiver.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권4호
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• pp.273-279
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• 2002

This paper presents a fabrication technology for the integration of single crystal Si microstructures with on-chip circuitry. It is a dissolved wafer technique that combines an electro-chemical etch-stop for the protection of circuitry with an impurity-based etch-stop for the microstructures, both of which are defined in an n-epi layer on a p-type Si wafer. A CMOS op. amp. has been integrated with $p^{++}$ Si accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have $3{\;}\mu\textrm{m}$ thick suspension beams and $15{\;}\mu\textrm{m}$ thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process. A variety of lead transfer methods are shown, and process details are discussed.

• 한국전기전자재료학회논문지
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• 제15권7호
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• pp.591-596
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• 2002

In this work, epitaxial GaN is grown on sapphire substrate in AlGaN/GaN heterostructures. Deliberate oxygen doping of GaN grown by MOVPE has been studied. The electron concentration increased as a function of the square root of the oxygen partial Pressure. Oxygen is a shallow donor with a thermal ionization energy of $27\pm2 meV$ measured by temperature dependent Hall effects. A compensation ratio of $\theta$=0.3~0.4 was determined from Hall effect measurements. The formation energy of $O_N$ of $E^F$ =1.3eV determined from the experimental data, is lower than the theoretically predicted vague.