• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.121-124
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• 2002

The proxy mechanism widely used in WWW systems offers low-delay data delivery by means of "proxy server". By applying the proxy mechanisms to the video streaming system, we expect that high-quality and low-delay video distribution can be accomplished without introducing extra load on the system. In addition, it is effective to adapt the quality of cached video data appropriately in the proxy if user requests are diverse due to heterogeneity in terms of the available bandwidth, end-system performance, and user′s preferences on the perceived video quality. We have proposed proxy caching mechanisms to accomplish the high-quality and highly-interactive video streaming services. In our proposed system, a video stream is divided into blocks for efficient use of the cache buffer. The proxy server is assumed to be able to adjust the quality of a cached or retrieved video block to the request through video filters. In this paper, to verify the practicality of our mechanisms, we implemented them on a real system and conducted experiments. Through evaluations from several performance aspects, it was shown that our proposed mechanisms can provide users with a low-latency and high-quality video streaming service in a heterogeneous environment.

• Journal of Information Technology Services
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• v.10 no.4
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• pp.259-268
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• 2011

A robot education system by emulation based on Web can be efficiently used for understanding concept of robot assembly practice and control mechanism of robot by control programming. It is important to predict the path of the line tracer robot which has to be decided by the robot. Shortest Path Algorithm is a well known algorithm which searches the most efficient path between the start node and the end node. There are two related typical algorithms. Dijkstra Algorithm searches the shortest path tree from a node to the rest of the other nodes. $A^*$ Algorithm searches the shortest paths among all nodes. The delay time caused by turning the direction of navigation for the line tracer robot at the crossroads can give big differences to the travel time of the robot. So we need an efficient path determine algorithm which can solve this problem. Thus, It is necessary to analyze the overhead of changing direction of robot at multi-linked node to determine the next direction for efficient routings. In this paper, we reflect the real delay time of directional changing from the real robot. A speed based Dijkstra algorithm is proposed and compared with the previous ones to analyze the performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1371-1379
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• 2009

In this paper, we propose a new multi-path routing protocol to provide reliable and stable data transmission in MANET that is composed of high-mobility nodes. The new multi-path routing establishes the main route by the mechanism based on AODV, and then finds the backup route that node-disjoint from the main route by making add nodes in the main route not participate in it. The data transmission starts immediately after finding the main route. And the backup route search process is taking place while data is transmitted to reduce the transmission delay. When either of the main route or the backup route is broken, data is transmitted continuously through the other route and the broken route is recovered to node-disjoint route by the route maintenance process. The result of the simulation based on the Qualnet simulator shows that the backup route exists 62.5% of the time when the main route is broken. And proposed routing protocol improved the packet transmission rate by 2~3% and reduced the end-to-end delay by 10% compared with AODV and AODV-Local Repair.

• Journal of electromagnetic engineering and science
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• v.13 no.4
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• pp.224-232
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• 2013

This paper describes composite cavity-backed crossed scythe-shaped dipoles with wide-beam circularly polarized (CP) radiation for use in Global Navigation Satellite Systems. Each branch of the dipole arm contains a meander line, with the end shaped like a scythe to achieve a significant reduction in the size of the radiator. For dual-band operation, each dipole arm is divided into two branches of different lengths. The dipoles are crossed through a $90^{\circ}$ phase delay line of a vacant-quarter printed ring to achieve CP radiation. The crossed dipoles are incorporated with a cavity-backed reflector to make the CP radiation unidirectional and to improve the CP radiation beamwidth. The proposed antennas have broad impedance matching and 3-dB axial ratio bandwidths, as well as right-hand CP radiation with a wide-beamwidth and high front-to-back ratio.

• 전자공학회논문지 IE
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• v.45 no.1
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• pp.15-23
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• 2008

In this paper, an algorithm, that provisions absolute differentiation of packet delays is proposed, simulated, and implemented with VHDL on XPC 860 CPU based test board with an objective for enhancing quality of service (QoS) in future packet networks. It features a scheme that compensates the deviation for prediction on the traffic to be arrived continuously. It predicts the traffic to be arrived at the beginning of a time slot and measures the actual arrived traffic at the end of the time slot and derives the difference between them. The deviation is utilized to the delay control operation for the next time slot to offset it. As it compensates the prediction error continuously, it shows superior adaptability to the bursty traffic as well as the exponential traffic. It is demonstrated through both simulation and the real traffic test on the board that the algorithm meets the quantitative delay bounds and shows superiority to the traffic fluctuation in comparison with the conventional non-adaptive mechanism.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.6 s.348
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• pp.30-38
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• 2006

In this paper, an algerian that provisions absolute and proportional differentiation of packet delays is proposed with an objective for enhancing quality of service (QoS) in future packet networks. It features a scheme that compensates the deviation for prediction on the traffic to be arrived continuously It predicts the traffic to be arrived at the beginning of a time slot and measures the actual arrived traffic at the end of the time slot and derives the difference between them. The deviation is utilized to the delay control operation for the next time slot to offset it. As it compensates the prediction error continuously, it shows superior adaptability to the bursty traffic as well as the exponential traffic. It is demonstrated through simulation that the algorithm meets the quantitative delay bounds and shows superiority to the traffic fluctuation in comparison with the conventional non-adaptive mechanism.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.168-174
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• 2012

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.6A
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• pp.609-616
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• 2011

The Delay/Disruption Tolerant Network (DTN) is a network designed to operate effectively using the mobility and storage of intermediate nodes under no end-to-end guaranteed network. This new network paradigm is well-suited for networks which have unstable path and long latencies (e.g. interplanetary network, vehicular network). In this paper, we first found that each taxi has its own regularly visiting area and define this property as spatial regularity. We analyze 4000 taxi trace data in Shanghai and show the existence of spatial regularity experimentally. Based on a spatial regularity in urban environment, we present a new DTN routing method. We introduce a Weighted Center (WC) which represents spatial regularity of each node. Through the association with evenly distributed access points (APs) in urban environment, most of vehicles get their grid locations and calculate their WCs. Since our routing method only uses neighbors' WCs for building routing paths, it can be regarded as distributed and practical protocols. Our experiments involving realistic network scenarios created by the traces of about 1500 Shanghai taxies show that our routing method achieves the higher performance compared to ECT, LET by 10%~110%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1032-1039
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• 2022

In this paper, we designed and implemented a cavity bandpass filter combined with a cross-coupling equalizer structure to enhance Group delay for 5G mobile network repeater, which can replace the SAW (Surface Acoustic Wave) type bandwidth filter used in the existing mobile communication system. Using the 3D EM simulation tool (HFSS), the resonance frequency, the coupling coefficient between resonators, and external quality coefficient between resonators were calculated. Based on this, a 12th bandpass filter was constructed to have attenuation characteristics of more than 20dB at the edge end of both sides of the band with a metal cavity structure with a frequency band of 3500MHz to 3600MHz and bandwidth of 97.85MHz. The designed bandpass filter satisfies the group delay time requirement for the 5G mobile communication standard and the in-band and out-band frequency responses.

• Journal of IKEEE
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• v.17 no.2
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• pp.168-175
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• 2013

The delay times due to the propagating of data on PCB depend on the shape and length of interconnection lines when memory controllers and high speed memories are soldered on the PCB. The dependency on the placement and routing on the PCB requires redesign of I/O logic or reconfiguration of the memory controller after the delay time is measured if the controller is programmable. In this paper, we propose architecture of configuring logic for the delay time estimation by writing and reading test patterns while initializing the memories. The configuration logic writes test patterns to the memory and reads them by changing timing until the correct patterns are read. The timing information is stored and the configuration logic configures the memory controller at the end of initialization. The proposed method enables easy design of systems using PCB by solving the problem of the mismatching caused by the variation of placement and routing of components including memories and memory controllers. The proposed method can be applied to high speed SRAM, DRAM, and flash memory.