• Current Optics and Photonics
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• 제3권5호
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• pp.445-450
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• 2019

The influence of high-power laser diode (HPLD) emitter width on the device performance is investigated for 975-nm (In,Ga)(As,P)/(Al,Ga)As broad-area HPLDs, using self-consistent electro-thermal-optical simulation. To guarantee the simulation's accuracy, simulated results are matched with the measured results for a sample HPLD with fitting parameters. The influences of HPLD emitter width on temperature distribution, output power, and the beam product parameter (BPP) are analyzed for three different emitter widths of 50, 70, and $90{\mu}m$. It is found that a device with smaller emitter width exhibits both thermal rollover and thermal blooming at lower output power, but smaller BPP.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2009년도 추계학술대회 논문집
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• pp.355-358
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• 2009

This paper presents the technology of selective emitter for high efficiency crystalline silicon solar cell. The effect of selective emitter is analyzed by using the simulation program for solar cell, PC1D. The selective emitter shows better spectral response in short wavelength regions compared to homogeneous emitter. Therefore, the efficiency of solar cell with selective emitter can be improved by changing the sheet resistance from 60 $\Omega/\square$ to 120 $\Omega/\square$. In addition, the power loss of solar cell can be minimized by optimizing width and gap of the finger electrodes on the selective emitter.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권9호
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• pp.523-526
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• 2000

A dual gate trench emitter IGBT structure is proposed and studied numerically using the device simulator MEDICI. The on-state forward voltage drop latch-up current density turn-off time and breakdown voltage of the proposed structure are compared with those of the conventional DMOS-IGBT and trench gate IGBT structures. The proposed structure forms an additional channel and increases collector current level resulting in reduction of on -state forward voltage drop. In addition the trench emitter increases latch-up current density by 148% in comparison with that for the conventional DMOS-IGBT and by 83% compared with that for the trench gate IGBT without degradation in breakdown voltage when the half trench gate width(Tgw) and trench emitter depth(Ted) are fixed at $1.5\mum\; and\; 2\mum$, respectively

• Current Optics and Photonics
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• 제6권2호
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• pp.191-195
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• 2022

We investigate the lateral far-field pattern characteristics, including divergence angle change and far-field pattern analysis as output power increases, of narrow-emitter-width 850 nm GaAs/AlGaAs laser diodes (LDs). Each LD has a cavity of 1200 and 1500 ㎛ and narrow emitter width of 2.4 ㎛ for the top and 4.6 ㎛ for the bottom. The threshold currents are 35 and 40 mA, and L-I kinks appear at power levels of 326 and 403 mW, respectively. The divergence angle tends to increase due to the occurrence of first-order lateral mode and the thermal lensing effect. But with the L-I kink, the divergence angle decreases and the far-field pattern becomes asymmetric. This is due to coherent superposition between the fundamental and the first-order lateral mode. We provide detailed explanations for these observations based on high-power laser diode simulation results.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2008년도 춘계학술대회 논문집
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• pp.151-154
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• 2008

The field emission lamps have the advantages to their cold cathode-characteristic and the eco-friendly, We realized that the dual emitter system showed very simple structure which gate and cathode electrodes are formed on the same glass surface. In this paper, we reported the properties of dual emitters depended on variation of gate width and spacing for optimum panel structure. In combination of dual emitter structure and bi-polar driving, electron beam spreads more than normal gate structure or diode structure, and emission uniformity increased in dual emitter structure at 5"-diagonal.

• 전자공학회논문지A
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• 제32A권2호
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• pp.57-65
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• 1995

The effects of device geometry and layout on high speed performance such as current gain outoff frequency(f$_{T}$) and maximum oscillation frequency(f$_{max}$) are of very improtant for the scaling-down of geterojunction bipolar transistors(HBT$_{s}$). In this paper AlGaAs/GaAs HBTs are fabricated by MBE epitaxial growth and conventional mesa process, and the experimental data of emitter-base geometru dependency of HBT performance are presented in order to provide the quantitative information for optimum device structure design. It is shown that f$_{T}$ and f$_{max}$ are inversely proportional to the emiter stripe width, while the low emitter perimeter/area ratio is better to f$_{T}$ and worse ot f$_{max}$. It is also demonstrated the f$_{T}$ and f$_{max}$ are highly improved by the emitter-base spacing reduction resulting in less parsitic effects. As the result f$_{T}$ of 42GHz and f$_{max}$ of 23GHz are obtained for fabricated HBT with emitter area of 3${\times}20^{\mu}m^{2}$ and E-B spacing of 0.2$\mu$m.m.m.

• 반도체디스플레이기술학회지
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• 제16권1호
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• pp.65-69
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• 2017

This paper presents a Technology-CAD (TCAD) simulation of the characteristics of crystalline Si pillar array solar cells. The junction depth and the surface concentration of the solar cells were optimized to obtain the targeted sheet resistance of the emitter region. The diffusion model was determined by calibrating the emitter doping profile of the microscale silicon pillars. The dimension parameters determining the pillar shape, such as width, height, and spacing were varied within a simulation window from ${\sim}2{\mu}m$ to $5{\mu}m$. The simulation showed that increasing pillar width (or diameter) and spacing resulted in the decrease of current density due to surface area loss, light trapping loss, and high reflectance. Although increasing pillar height might improve the chances of light trapping, the recombination loss due to the increase in the carrier's transfer length canceled out the positive effect to the photo-generation component of the current. The silicon pillars were experimentally formed by photoresist patterning and electroless etching. The laboratory results of a fabricated Si pillar solar cell showed the efficiency and the fill factor to be close to the simulation results.

• 대한전자공학회논문지SD
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• 제44권8호
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• pp.8-15
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• 2007

본 논문에서는 산화된 다공질 폴리실리콘을 이용하여 전계 방출 소자를 제작하여, 각각의 픽셀에 따른 전기적 특성과 형광체의 발광 특성을 조사하였다. 실제 대면적 디스플레이 소자에 적용하기 위해서 PM 방식을 이용해서 소자를 픽셀별로 동작하였고, 상부금속 전극의 어레이에 따른 두께와 폭의 공정조건을 확립하였다. 산화된 다공질 폴리실리콘의 미세 구조를 분석하고, 각각의 픽셀에 따른 전계방출 특성을 조사해 보았다. 상부금속 전극의 두께와 폭에 따른 전자방출 특성을 조사해 본 결과 Ti/pt(2nm/7nm)가 가장 적절한 두께라는 것을 확인 할 수 있었고, 2.5 mm 이상 폭에서 전자방출 효율이 증가하는 모습을 확인 할 수 있었다. 각 픽셀에 따른 소자의 전기적 특성은 픽셀마다 조금씩의 차이는 있지만 거의 동일한 누설 전류와 방출 전류가 나타남을 확인할 수 있었고, 동일한 크기의 효율도 관찰할 수 있었다. 누설 전류와 방출 전류는 시간이 증가함에 따라 감소하는 모습이 나타나긴 하였으나, 모든 픽셀이 거의 동일하게 감소하였다. 각각의 픽셀에 따른 휘도는 큰 차이가 없음을 확인할 수 있었고, 20 V에서 $700cd/m^2$ 이상의 높은 휘도를 나타내었으므로 실제 디스플레이 소자로도 응용이 가능할 것이다.

• 대한전자공학회논문지
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• 제27권1호
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• pp.51-58
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• 1990

NPN Si bipolar transistors with two different emitter widths are designed and fabricated. The effects of the emitter width on the small signal parameters of BJTs are measured and discussed. A new ac method for determining the current gain, the cut off frequency and the internal capacitances from the input impedance circle characteristics as a function of the varied external series resistances is presented. This method allows an accurate characterization of bipolar transistors with high current gain. The variation of the I-V curves of the emitter junction with the reverse collector junction voltages is discussed from the changes in the intsrinsic base resistances.

• 전기전자학회논문지
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• 제25권2호
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• pp.350-355
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• 2021

IGBT는 MOSFET과 BJT의 구조를 동시에 포함하고 있는 전력반도체 소자이며, MOSFET의 빠른 스위칭 속도와 BJT의 고 내압, 높은 전류내량 특성을 갖고 있다. GBT는 높은 항복전압, 낮은 V_CE-SAT, 빠른 스위칭 속도, 고 신뢰성의 이상적인 파워 반도체 소자의 요구사항을 목표로 하는 소자이다. 본 논문에서는 1,200V 급 Trench Gate Field Stop IGBT의 상단 공정 파라미터인 Gate oxide thickness, Trench Gate Width, P+ Emitter width를 변화시키면서 변화하는 Eoff, V_CE-SAT을 분석하였고, 이에 따른 최적의 상단 공정 파라미터를 제시하였다. Synopsys T-CAD Simulator를 통해 항복전압 1,470V와 V_CE-SAT 2.17V, Eon 0.361mJ, Eoff 1.152mJ의 전기적 특성을 갖는 IGBT 소자를 구현하였다.