• Journal of the Korean Society of Safety
• /
• v.14 no.3
• /
• pp.69-77
• /
• 1999

As the use of automatic handling equipment for sensitive semiconductor devices is rapidly increased, manufacturers of electronic components and equipment need to be more alert to the problem of electrostatic discharges(ESD). Semiconductor devices such as IC, LSI, VLSI become a high density pattern of being more fragile by ESD phenomena. One of the most common causes of electrostatic damage is the direct transfer of electrostatic charge from the human body or a charged material to the electrostatic discharge sensitive devices. Accordingly, characteristics of electrostatic attenuation in domestic semiconductor devices is investigated to evaluate the ESD phenomina in the semiconductors in this paper. The required data are obtained by Static Honestmeter. Also The results in this paper can be used for the prevention of semiconductor failure by ESD.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.12
• /
• pp.88-97
• /
• 1993

Electrostatic Discharge(ESD) is one of the major reliability, issues for today's VLSI production. Since the gate oxide with a thickness of 100~300$\AA$ is vulnerable to several thousand volt of ESD surge, it is necessary to control the ESD events and design an efficient protection circuit. In this paper, physical mechanism of the catastrophic ESD damage is investigated by transient analysis based upon Human Body Model(HBM). Using two-dimensional electrothermal simulator, we study the failure mechanism of the output protection devices by ESD and discuss the design issues for the optimun protection network.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.16 no.1 s.106
• /
• pp.75-80
• /
• 2006

This paper introduces the mechanism of the ESD(electrostatic discharge) in the HDD spindle system using FDBs(fluid dynamic bearings). When a HDD(hard disk drive) spindle system is rotating, triboelectric charging occurs in the FDBs through the friction between the lubricant and the rotating shaft or between the lubricant and stationary sleeve. And this electrostatic charge is accumulated in the rotating parts of the HDD spindle system because they are insulated from the ground by the lubricant. This research shows experimentally that the behavior of electric charge and discharge in the FDB spindle system is the same as that of a capacitor. It also measures the electrostatic voltage difference between the rotating and stationary parts in the FDB spindle system due to the change of humidity, supporting load and motor speed. This research shows that the control of ESD is required in the HDD spindle system using FDBs, because the electrostatic charge accumulated in the FDB spindle system may cause the breakdown damage of the GMR head and data loss consequently.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.3
• /
• pp.6-21
• /
• 2008

We have investigated the effect of the forward and reverse ESD pulse accumulation on the development of the oxide VCSEL's electrical and optical characteristics. The forward ESD-induced degradation is complicated, showing three degradation phases with increasing ESD voltage while the reverse ESD-induced degradation is divided by a sudden distinctive change in elecorl-optical characteristics. By comparing the measured L-I-V characteristics and their derivatives with the fitted characteristics using an equivalent circuit model as well as the large signal circuit model, the development of the oxide VCSEL's electro-optical characteristics under forward and reverse ESD conditions has been fully understood.

• Journal of Satellite, Information and Communications
• /
• v.8 no.4
• /
• pp.124-129
• /
• 2013

An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latch-up problem during normal operation. However, a modified NSCR_PPS device with counter pocket source(CPS) and partial p-type well(PPW) structure demonstrates highly latch-up immune current-voltage characteristics.

• ETRI Journal
• /
• v.39 no.5
• /
• pp.746-755
• /
• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.3
• /
• pp.339-344
• /
• 2014

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.3-4
• /
• 2009

As device process technology advances, effective channel length, the thickness of gate oxide, and supply voltage decreases. This paper describes a novel electrostatic discharge (ESD) protection device which has current feedback for high ESD immunity. A conventional Gate-Grounded NMOS (GGNMOS) transistor has only one ESD current path, which makes, the core circuit be in the safe region, so an GGNMOS transistor has low current immunity compared with our device which has current feedback path. To simulate our device, we use conventional $0.18\;{\mu}m$ technology parameters with a gate oxide thickness of $43\;{\AA}$ and power supply voltage of 1.8 V. Our simulation results indicate that the area of our ESD protection, device can be smaller than a GGNMOS transistor, and ESD immunity is better than a GGNMOS transistor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.27 no.11
• /
• pp.686-689
• /
• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• 한국정보통신설비학회:학술대회논문집
• /
• 2006.08a
• /
• pp.208-211
• /
• 2006

In this paper, a tunable image rejection filter using two varactors is developed for mobile convergence. The filter is fabricated on a 0.25um substrate. ESD Pad is embedded to prevent damage caused by electrostatic discharge(ESD). Bias voltages are at WCDMA(2.1GHz). WiBro(2.3GHz), and WLAN(2.45) are 0.5V, 0.95V and 1.8V respectively. And the image rejection rations are more than 28dB at each band and insertion losses are less than 2dB at each band.