• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.163-193
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• 1999

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.7-14
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• 2015

Research and application of three dimensional packaging technology in electronics have been increasing according to the trend of high density, high capacity and light weight in electronics. In this paper, TSV fabrication and research trend in three dimensional packaging are reported. Low alpha solder bumping which can solve the soft error problem in electronics is also introduced. In detail, this paper includes fabrication of TSV, functional layers deposition, Cu filling in TSV by electroplating using PPR (periodic pulse reverse) and 3 step PPR processes, and low alpha solder bumping on TSV by solder ball. TSV and low alpha solder bumping technologies need more studies and improvements, and the drawbacks of three dimensional packaging can be solved gradually through continuous attentions and researches.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.13-21
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• 2014

Technology for high power devices has made impressive progress in increasing the current density of power semiconductor, system module, and design optimization, which realize high power systems with heterogeneous functional integration. Depending on the performance development of high power semiconductor, packaging technology of high power device is urgently required for efficiency improvement of the device. Power device packaging must provide superior thermal management due to high operating temperature of power modules. Here we, therefore, review critical challenges of typical power electronics packaging today including core assembly processes, component materials, and reliability evaluation regulations.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.11a
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• pp.125-128
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• 1999

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.11a
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• pp.131-135
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• 1999

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.7
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• pp.407-412
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• 2017

This paper introduces a biocompatible packaging system for implantable medical device having a hermetic sealing, such that a perfect physical and chemical isolation between electronic medical system and human body (including tissue, body fluids, etc.) is obtained. The hermetic packaging includes an electronic MEMS pressure sensor, power charging system, and bluetooth communication system to wirelessly measure variation of capacitance. The packaging was acquired by Quartz direct bonding and $CO_2$ laser welding, with a size of width $ 6cm{\times}length\;10cm{\times}lheight\;3cm$. Hermetic sealing of the packaged system was tested by changing the pressure in a hermetic chamber using a precision pressure controller, from atmospheric to 900 mmHg. We found that the packaged system retained the same count or capacitance values with sensor 1 - 25,500, sensor 2 - 26,000, and sensor 3 - 20,800, at atmospheric as well as 900 mmHg pressure for 5 hours. This result shows that the packaging method has perfect hermetic sealing in any environment of the human body pressure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.338-339
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• 2008

현재 PCB (Printed circuit board) 산업은 디스플레이, 모바일 시장의 수요 증가로 인해 활성화 되면서 다앙한 분야로 확대 되어가고 있다. 전자기기의 직접화, 고속파, 사용 주파수 영역의 증가로 인해 수십 GHz 영역에서도 활용이 가능한 소재 및 기판의 필요성이 대두되어 지고 있어 이에 대응할 수 있는 소재 개발도 다양해지고 있다. 본 논문에서는 GHz 영역에서 인쇄회로기판의 회로형태가 특성에 미치는 영향에 대해 연구하였다. 이를위해 패턴도금법과 에칭법으로 회로를 형성하였다. 패턴도금법으로 형성된 시편은 무전해 구리도금 공정을 거친 후 감광성 필름을 이용하여 전해 도금방법을 패턴을 형성하여 회로를 구현하였고, 에칭 패턴 시편은 FR4를 이용하여 동박접합과 도금 공정 후 마스크 패턴을 사용하여 노광, 현상, 에칭 공정을 거쳐 회로를 구성하였다. GHz영역에서 Transmission Line 특성을 분석하였으며 구리 패턴과 절연체사이의 계면형태가 특성에 영향을 주는 것을 확인할 수 있었다.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.1
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• pp.7-14
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• 2015

Recently, advances in nano-material researches have opened the door for various transparent conductive materials, which include carbon nanotube, graphene, Ag and Cu nanowire, and printable metal grids. Among them, Ag nanowires are particularly interesting to synthesize because bulk Ag exhibits the highest electrical conductivity among all metals. Here we reviewed recently-published research works introducing various devices from organic light emitting diode to tactile sensing devices, all of which are employing AgNW for a conducting material. They proposed methods to enhance the stretchability and reversibility of the transparent electrodes, and apply them to make various flexible and stretchable electronics. It is expected that Ag nanowires are applicable to a wide range of high-performance, low-cost, stretchable electronic devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.357-358
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• 2005

Compact power amplifier modules (PAM) for WCDMA/KPCS and GSM/WCDMA dual-band applications based on multilayer low temperature co-fired ceramic (LTCC) substrates are presented in this paper. The proposed modules are composed of an InGaP/GaAs HBT PAs on top of the LTCC substrates and passive components such as RF chokes and capacitors which are embedded in the substrates. The overall size of the modules is less than 6mm $\times$ 6mm $\times$ 0.8mm. The measured result shows that the PAM delivers a power of 28 dBm with a power added efficiency (PAE) of more than 30 % at KPCS band. The adjacent-channel power ratio (ACPR) at 1.25-MHz and 2.25-MHz offset is -44dBc/30kHz and -60dBc/30kHz, respectively, at 28-dBm output power. Also, the PAM for WCDMA band exhibits an output power of 27 dBm and 32-dB gain at 1.95 GHz with a 3.4-V supply. The adjacent-channel leakage ratio (ACLR) at 5-MHz and 10-MHz offset is -37.5dBc/3.84MHz and -48dBc/3.84MHz, respectively. The measured result of the GSM PAM shows an output power of 33.4 dBm and a power gain of 30.4 dB at 900MHz with a 3.5V supply. The corresponding power added efficiency (PAE) is more than 52.6 %.

• Electronics and Telecommunications Trends
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• v.39 no.3
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• pp.98-106
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• 2024

Advanced packaging is emerging as a core technology owing to the increasing demand for multifunctional and highly integrated semiconductors to achieve low power and high performance following digital transformation. It may allow to overcome current limitations of semiconductor process miniaturization and enables single packaging of individual devices. The introduction of advanced packaging facilitates the integration of various chips into one device, and it is emerging as a competitive edge in the industry with high added value, possibly replacing traditional packaging that focuses on electrical connections and the protection of semiconductor devices.