• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.536-539
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• 2002

In this paper, we developed the automatic optical fiber aligner by image processing and automatic loading system. Optical fiber is indispensable for optical communication systems that transmit large volumes of data at high speed, but super-precision technology in sub-micron units is required for optical axis adjustment, we have developed 6-axis micro stage system for I/O optical fiber arrays, the initial automatic aligning system/software for a input optical array by the image processing technique, fast I/O-synchronous aligning strategy, the automatic loading/unloading system and the automatic UV bonding mechanism. In order to adjust the alignment it used on PC based motion controller, a $10\mu\textrm{mm}$ repeat-detailed drawing of automatic loading system is developed by a primary line up for high detailed drawing. Also, at this researches used the image processing system and algorithm instead of the existing a primary hand-line up. and fiber input array and waveguide chip formed in line by automatic. Therefore, the developed and manufactured optical aligning system in this research fulfills the great role of support industry for major electronics manufacturers, telecommunications companies, universities, government agencies and other research institutions.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.8
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• pp.3103-3120
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• 2015

This paper presents a single-phase energy metering chip with built-in calibration function to measure electric power quantities. The entire chip consists of an analog front end, a filter block, a computation engine, a calibration engine, and an external interface block. The key design issues are how to reduce the implementation costs of the computation engine from repeatedly used arithmetic operations and how to simplify calibration procedure and reduce calibration time. The proposed energy metering chip simplifies the computation engine using time-division multiplexed arithmetic units. It also provides a simple and fast calibration scheme by using integrated digital calibration functionality. The chip is fabricated with 0.18-μm six-layer metal CMOS process and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4096 kHz and consumes 9.84 mW in 3.3 V supply.

• Solar Energy
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• v.20 no.4
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• pp.45-52
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• 2000

Multi A/C is consisted of one outdoor unit and several indoor units. When the Multi Air conditioner is installed, we have to be cautious of the length of pipe arrangements. When the pipe arrangement is installed with unbalance or too long, there can be cooling capacity losses and low EER. An experimental study was carried out about the operation characteristic of Multi Air conditioner varying the length of pipe arrangements. If the pipe arrangement of the system is 15m, the cooling capacity and EER were decreased 0.8% and 1.3% respectively compared to the case when pipe arrangement is 5m. In case of 25m, the cooling capacity and EER were decreased 10.7% and 12.2% respectively compared to the case of 5m. When the length of pipe is not same each other, it is profitable to make the pipe length of highest capacity indoor unit shortest.

• Proceedings of the KOSOMBE Conference
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• v.1995 no.05
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• pp.164-166
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• 1995

The objectives of study are to develop a peripheral device on the endoscopic surgery system. These systems are consist of the following units. They are a color monitor of high resolution, light source, computer system and endoscopic camera with a C-mount head, irrigator, color video printer, Super VHS recorder and a system rack. The color monitor is a NTSC monitor for monitoring the image projected of the surgical section. The lightsource is necessary to irradiate the interior of a body via an optic fiber, The light projector will adapt the brightness in accordance with changing distance from the object. A miniature camera using a color CCD chip and computer system is used to capture and control an image of the surgical section[1]. The video printer is a 300 DPI resolution using thermal sublimation methods, which is developed by Samsung Electronics Co., Ltd. The specification of the endoscopic data management system is consist of storage of a captured image and pathological database of patients [2-4].

• ETRI Journal
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• v.37 no.6
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• pp.1199-1210
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• 2015

Automatic emotion recognition based on facial cues, such as facial action units (AUs), has received huge attention in the last decade due to its wide variety of applications. Current computer-based automated two-phase facial emotion recognition procedures first detect AUs from input images and then infer target emotions from the detected AUs. However, more robust AU detection and AU-to-emotion mapping methods are required to deal with the error accumulation problem inherent in the multiphase scheme. Motivated by our key observation that a single AU detector does not perform equally well for all AUs, we propose a novel two-phase facial emotion recognition framework, where the presence of AUs is detected by group decisions of multiple AU detectors and a target emotion is inferred from the combined AU detection decisions. Our emotion recognition framework consists of three major components - multiple AU detection, AU detection fusion, and AU-to-emotion mapping. The experimental results on two real-world face databases demonstrate an improved performance over the previous two-phase method using a single AU detector in terms of both AU detection accuracy and correct emotion recognition rate.

• Proceedings of the IEEK Conference
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• summer
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• pp.204-208
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• 2004

Embedded business will be expanded market more and more since customers seek more wearable and ubiquitous systems. Cellular telephones, PDAs, notebooks and portable multimedia devices could bring higher microprocessor revenues and more rewarding improvements in performance and functions. Increasing battery capacity is still creeping along the roadmap. Until a small practical fuel cell becomes available, microprocessor developers must come up with power-reduction methods. According to MPR 2003, the instruction and data caches of ARM920T processor consume $44\%$ of total processor power. The rest of it is split into the power consumptions of the integer core, memory management units, bus interface unit and other essential CPU circuitry. And the relationships among CPU, peripherals and caches may change in the future. The processor working on higher operating frequency will exact larger cache RAM and consume more energy. In this paper, we propose advanced low power trace cache which caches traces of the dynamic instruction stream, and reduces cache access times. And we evaluate the performance of the trace cache and estimate the power of the trace cache, which is compared with conventional cache.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.391-406
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• 2014

The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.

• ETRI Journal
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• v.30 no.4
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• pp.576-586
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• 2008

In most parallel loops of embedded applications, every iteration executes the exact same sequence of instructions while manipulating different data. This fact motivates a new compiler-hardware orchestrated execution framework in which all parallel threads share one fetch unit and one decode unit but have their own execution, memory, and write-back units. This resource sharing enables parallel threads to execute in lockstep with minimal hardware extension and compiler support. Our proposed architecture, called multithreaded lockstep execution processor (MLEP), is a compromise between the single-instruction multiple-data (SIMD) and symmetric multithreading/chip multiprocessor (SMT/CMP) solutions. The proposed approach is more favorable than a typical SIMD execution in terms of degree of parallelism, range of applicability, and code generation, and can save more power and chip area than the SMT/CMP approach without significant performance degradation. For the architecture verification, we extend a commercial 32-bit embedded core AE32000C and synthesize it on Xilinx FPGA. Compared to the original architecture, our approach is 13.5% faster with a 2-way MLEP and 33.7% faster with a 4-way MLEP in EEMBC benchmarks which are automatically parallelized by the Intel compiler.

• ETRI Journal
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• v.38 no.1
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• pp.1-8
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• 2016

A large incoherent crosstalk (IC) caused by amplified spontaneous emission (ASE) noise power from Tx-disabled optical network units and a differential path loss has been shown to degrade upstream transmission performance in time-division multiplexing passive optical networks. This paper considers the IC-induced power penalty of an upstream signal both in an XG-PON and in a TWDM-PON. We investigate the degradation of the extinction ratio and relative intensity noise through a simulation and experiments. For the XG-PON case, we observe a 9.6 dB difference in the level of ASE noise power from Tx-disabled ONUs (hereafter known simply as ASE noise) between our result and the ITU-T XG-PON PMD recommendation. We propose an optical filtering method to mitigate an IC-induced power penalty. In the TWDM-PON case, the IC-induced power penalty is naturally negligible because the ASE noise is filtered by a wavelength multiplexer at the optical line terminal. The results provide design guidelines for the level of ASE noise in both XG-PONs and TWDM-PONs.

• ETRI Journal
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• v.38 no.1
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• pp.185-194
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• 2016

In this paper, a novel rate control scheme for low delay video coding of High Efficiency Video Coding (HEVC) is proposed. The proposed scheme is developed by considering a new temporal prediction structure of HEVC. In the proposed scheme, the relationship between bit rate and quantization step is exploited firstly to formulate an accurate quadratic rate-quantization (R-Q) model. Secondly, a method of determining the quantization parameters (QPs) for the first frames within a group of pictures is proposed. Thirdly, an accurate frame-level bit allocation method is proposed for HEVC. Finally, based on the proposed R-Q model and the target bit allocated for the frame, the QPs are predicted for coding tree units by using rate-distortion (R-D) optimization. We compare our scheme against that of three other state-of-the-art rate control schemes. Experimental results show that the proposed rate control scheme can increase the Bjøntegaard delta peak signal-to-noise ratio by 0.65 dB and 0.09 dB on average compared with the JCTVC-I0094 and JCTVC-M0036 schemes, respectively, both of which have been implemented in an HEVC test model encoder; furthermore, the proposed scheme achieves a similar R-D performance to Wang's scheme, as well as obtaining the smallest bit rate mismatch error of all the schemes.