• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.1
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• pp.63-67
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• 2008

The charged particle type display is a kind of electronic paper showing information images using positive and negative charged particles ($<10{\mu}m$). In this work we used yellow(-) and black(+) particles which are respectively addressed to the cells of a upper and a rear substrate by using electric field. Our independent addressing method has strong points compared to the mixed particle putting method. The packaging with two orthogonal substrates and the aging process is followed by addressing process. The panel is sequentially driven by matrix method for each 4-unit cells. Layers of particles are controlled by barrier ribs and must be addressed to minimum 2 layers.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.352-356
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• 2007

The Ni/Cr/Al/Cu (51/41/4/4 wt%) thin films were deposited by using DC magnetron sputtering method for the application of the resistors having low TCR (temperature coefficients of resistance) and high resistivity from the former printed-results[3]. The TCR values measured on the as-deposited thin film resistors were less than ${\pm}10\;ppm/^{\circ}C$ and $-6{\sim}+1\;ppm/^{\circ}C$ after annealing and packaging process. The TCR values were $-3{\sim}1\;ppm/^{\circ}C$ (ratio of variation : about 0.02 %) and $-30{\sim}20\;ppm/^{\circ}C$ (ratio of variation : about $0.5{\sim}1\;%$) for the thermal cycling and PCT (pressure cooker test), respectively. It was confirmed that the reliability properties of the thin film resistor were good for electronic components.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.15-22
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• 2019

Metallic nanowires (MNWs) have recently been considered as one of the most promising candidates for flexible electrodes of advanced electronics including wearable devices, electronic skins, and soft robotics, since they have high aspect ratio in physical shape, low percolation threshold, high ductility and optical transparency. Herein, we review the latest findings related to the MNWs and discuss the properties and potentials of this material that can be used in implementation of various advanced electronic devices.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.167-170
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• 2021

Integrated passive device (IPD) technology has emerged with the need for 5G. In order to integrate and miniaturize capacitors inside IPD, various studies are actively performed using high-k materials and trench structures. In this paper, an EM(Electromagnetic) simulation study was performed by applying an oxide dielectric to the capacitors having a various trench type structures. Commercially available materials HfO₂, Al₂O₃, and Ta₂O₅ are applied to non, circle, trefoil, and quatrefoil type trench structures to confirm changes in each material or structure. As a result, the bigger the capacitor area and the higher dielectric constant of the oxide dielectric, the insertion loss tended to decrease.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.308-312
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• 2003

The packaging of the integrated circuits requires knowledge of ceramics and metals to accommodate the fabrication of modules that are used to construct subsystems and entire systems from extremely small components. Composite ceramics ($Al_2O_3-SiO_2$) were tested for substrates. A stress analysis was conducted for a linear work-hardening metal cylinder embedded in an infinite ceramic matrix. The bond between the metal and ceramic was established at high temperature and stresses developed during cooling to room temperature. The calculations showed that the stresses depend on the mismatch in thermal expansion, the elastic properties, and the yield strength and work hardening rate of the metal. Experimental measurements of the surface stresses have also been made on a $Cu/Al_2O_3-SiO_2$ ceramic system, using an indentation technique. A comparison revealed that the calculated stresses were appreciably larger than the measured surface stresses, indicating an important difference between the bulk and surface residual stresses. However, it was also shown that porosity in the metal could plastically expand and permit substantial dilatational relaxation of the residual stresses. Conversely it was noted that pore clusters were capable of initiating ductile rupture, by means of a plastic instability, in the presence of appreciable tri-axiality. The role of ceramics for packaging of microelectronics will continue to be extremely challenging.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.3-6
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• 2004

Power semiconductor devices are being compact, high performance and intelligent thanks to recent remarkable developments of silicon design, process and related packaging technologies. Developments of MOS-gate transistors such as MOSFET and IGBT are dominant thanks to their advantages on high speed operation. In conjunction with package technology, silicon technologies such as trench, charge balance and NPT will support future power semiconductors. In addition, wide band gap material such as SiC and GaN are being studies for next generation power semiconductor devices.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.49-53
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• 2004

Polymeric materials are widely used in the electronic industry as a common dielectric material or adhesive. The polymeric layer coated on Si substrate can be subjected to thermal stresses due to difference in thermal expansion coefficients. The mismatch in thermal properties between the polymeric layer and the substrate results in significant residual stresses. In this study, the thermal deformation is measured by a curvature measurement method using laser scanning, and the elastic modulus is calculated by an analytic model.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.37 no.9
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• pp.1151-1158
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• 2013

Knowledge of the moisture sorption properties of a material is essential for optimal material development and analysis of the delamination failure caused by vapor pressure at the interlayer during the manufacturing process of integrated packaging devices. In this paper, both temperature dependent absorption and desorption properties according to temperature and humidity model are parameterized and the effects of water activities and temperature are discussed. The activation energy obtained from the parameterized diffusivity determines the acceleration factor for the equivalency of moisture sorption levels, which enables the effect of moisture diffusivity on the equivalent elapsed testing time required for evaluating the reliable life time to be estimated. The acceleration factor evaluated at the reliability testing standard of the flexible packaging module is exampled.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.83-89
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• 2014

Solder paste plays a crucial role as the widely used joining material in surface mount technology (SMT). The understanding of its behaviour and properties is essential to ensure the proper functioning of the electronic assemblies. The composition of the solder paste is known to be directly related to its rheological behaviour. This paper provides a brief overview of the solder paste behaviour of four different solder paste formulations, stencil printing processes, and techniques to characterize solder paste behaviour adequately. The solder pastes are based on the Sn-3.0Ag-0.5Cu alloy, are different in their particle size, metal content and flux system. The solder pastes are characterized in terms of solder particle size and shape as well as the rheological characterizations such as oscillatory sweep tests, viscosity, and creep recovery behaviour of pastes.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.