• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.6
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• pp.1219-1226
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• 2017

In this paper, it is performed the optimal design of the UV LED bar which can be used variously. The UV LED Bar emits ultraviolet rays, so it is important to emit ultraviolet rays constantly for the purpose of use. In order to emit a certain amount of ultraviolet rays as ever, the ultraviolet ray emission should be driven by a constant current source within the operable input voltage range. And also the heat dissipation is particularly important because of the long ultraviolet emission retention time due to the UV utilization characteristics. In addition, since human body protection is essential, the algorithm is configured to operate according to human body detection using distance sensor and Bluetooth. Three 365nm UV LEDs were used in series to emit ultraviolet UVA, operating at the constant current of 500mA with an efficiency of 87.5% and a power consumption of 6.006W. The ultraviolet radiation dose was measured at $5.35mW/cm^2$ at the distance of 10 cm when measured by the Lutron ultraviolet measuring instruments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.689-691
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• 2010

This study is the visually identification lighting for easy to distinguish using colors LED on AtoN facility in harbor gate, which have realized a controller for certainly express the gate of harbor by red light and green light of both sides a harbor and for synchronization at a time of right and left or sequential the harbor guidance light through synchronizer or timer by GPS. There is expectation effect that is prevent a confusion about distinguish of facility by ship's operator and to beautify a night scene of harbor, which is expressed to identification lighting differ from great many lighting of harbor with variable color lighting the lighthouse body and vertical layer color lighting using LED. Especially the function of AtoN is displayed for harbor safety message by CW lighting, and this system is the power consumption greatly reduce by candle alternated high light LED.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.68-73
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• 2013

In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.5
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• pp.50-60
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• 2010

For the last half a century, the personal computer and software industries have been prosperous due to the incessant evolution of computer systems. In the 21st century, the embedded system market has greatly increased as the market shifted to the mobile gadget field. While a lot of multimedia gadgets such as mobile phone, navigation system, PMP, etc. are pouring into the market, most industrial control systems still rely on 8-bit micro-controllers and simple application software techniques. Unfortunately, the technological barrier which requires additional investment and higher quality manpower to overcome, and the business risks which come from the uncertainty of the market growth and the competitiveness of the resulting products have prevented the companies in the industry from taking advantage of such fancy technologies. However, high performance, low-power and low-cost hardware and software platforms will enable their high-technology products to be developed and recognized by potential clients in the future. This paper presents such a platform for industrial embedded systems. The platform was designed based on Telechips TCC8300 multimedia processor which embedded a variety of parallel hardware for the implementation of multimedia functions. And open-source Embedded Linux, TinyX and GTK+ are used for implementation of GUI to minimize technology costs. In order to estimate the expected performance and power consumption, the performance improvement and the power consumption due to each of enabled hardware sub-systems including YUV2RGB frame converter are measured. An analytic model was devised to check the feasibility of a new application and trade off its performance and power consumption. The validity of the model has been confirmed by implementing a real target system. The cost can be further mitigated by using the hardware parts which are being used for mass production products mostly in the cell-phone market.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.5
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• pp.851-858
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• 2021

Due to the increase in renewable energy and distributed resources, not only traditional data but also various energy-related data are being generated in the new energy industry. In other words, there are various renewable energy facilities and power generation data, system operation data, metering and rate-related data, as well as weather and energy efficiency data necessary for new services and analysis. Energy big data processing technology can systematically analyze and diagnose data generated in the first half of the power production and consumption infrastructure, including distributed resources, systems, and AMI. Through this, it will be a technology that supports the creation of new businesses in convergence between the ICT industry and the energy industry. To this end, research on the data analysis system, such as itemized characteristic analysis of the collected data, correlation sampling, categorization of each feature, and element definition, is needed. In addition, research on data purification technology for data loss and abnormal state processing should be conducted. In addition, it is necessary to develop and structure NIFI, Spark, and HDFS systems so that energy data can be stored and managed in real time. In this study, the overall energy data processing technology and system for various power transactions as described above were proposed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.53-60
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• 2009

A low-power/small-area 128-point FFT processor is designed, which is based on logarithmic number system (LNS) and some design techniques to minimize both hardware complexity and arithmetic error. The complex-number multiplications and additions/subtractions for FFT computation are implemented with LNS adders and look-up table (LUT) rather than using conventional two's complement multipliers and adders. Our design reduces the gate counts by 21% and the memory size by 16% when compared to the conventional two's complement implementation. Also, the estimated power consumption is reduced by about 18%. The LNS-based FFT processor synthesized with 0.35 ${\mu}m$ CMOS standard cell library has 39,910 gates and 2,880 bits memory. It can compute a 128-point FIT in 2.13 ${\mu}s$ with 60 MHz@2.5V, and has the average SQNR of 40.7 dB.

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.13-20
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• 2010

This paper describes a current mode PWM DC-DC converter IC for battery charger and supply power converter for portable electronic devices. The maximum supply voltage of IC is 40[V] and 2.8[V]~330[V] DC input power is converted to higher or programmed DC voltage according to external resistor ratio or wire winding ratio of transformer. The maximum supply output current is 3[A] over and voltage error of output node is within 3[%]. The whole circuit needed current mode PWM DC-DC converter circuit is designed. The package dimensions and number of external parts are minimized in order to get a smaller hardware size. The power consumption is smaller then 1[mW] at stand by period with supply voltage of 3.6[V] and maximum energy conversion efficiency is about 86[%]. This device has been designed in a 0.6[um] double poly, double metal 40[V] CMOS process and whole chip size is 2100*2000 [um2].

• ETRI Journal
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• v.36 no.3
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• pp.352-360
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• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.

• Journal of the Korean Society of Industry Convergence
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• v.17 no.4
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• pp.234-244
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• 2014

Recently it has been focused that the automobile engine has developed in a strong upward tendency for the use of the high viscosity and poorer quality fuels in achieving the high performance, fuel economy, and emission reduction. Therefore it is not easy to solve the problems between low specific fuel consumption and exhaust emission control at motor cars. In this study, it is designed and used the engine test bed which is installed with turbocharger and intercooler. In addition to equipped using CRDI by controlling injection timing with mapping modulator, it has been tested and analyzed the engine performance, combustion characteristics, and exhaust emission as operating parameters, and they were engine speeds(rpm), injection timing(bTDC), and engine load(%). From the result of an experimental analysis, peak cylinder pressure and the rate of pressure rise were increased, and the location of it was closer toward top dead center according to the increasing of engine speed and load, and with advancing injection timing. The combustion characteristics are effected by fuel injection timing due to be enhanced the mass burned fraction. Using the engine dynamometer for analyzing the engine performance, the engine torque and power have been enhanced according to advancing the fuel injection timing. In analyzing of exhaust emission, there has been a trade-off between PM and NOx with increasing of engine speed and load, and with advanced injection timing. The experimental data are shown that the formation of NOx has increased and PM, vice versa.