• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.65-70
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• 2008

In FIR filter design, multipliers occupy most of the area. To efficiently reduce the area occupied by multipliers, Common Subexpression Elimination (CSE) algorithm can be used instead of separate multipliers. However, the filter computation time can be increased due to the long carry propagation in CSE circuits. More specifically, when the difference of weights between the two inputs to an adder in CSE circuits is large, long carry propagation time is required due to large sign extension. In this paper, we propose a sign-extension reduction method in common subexpression elimination circuit. By Synopsys simulation using Samsung 0.35um library, it is shown that the proposed method leads to 17%, 31% and 12% reduction in the area, time delay and power consumption, respectively, compared with conventional method.

• Journal of IKEEE
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• v.23 no.4
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• pp.1257-1264
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• 2019

A 3-GSymbol/s/lane transceiver, which supports the mobile industry processor interface (MIPI) C-physical layer (PHY) specification version 1.1, is proposed. It performs channel mismatch correction to improve the signal integrity that is deteriorated by using three-level signals over three channels. The proposed channel mismatch correction is performed by detecting channel mismatches in the receiver and adjusting the delay times of the transmission data in the transmitter according to the detection result. The channel mismatch detection in the receiver is performed by comparing the phases of the received signals with respect to the pre-determined data pattern transmitted from the transmitter. The proposed MIPI C-PHY receiver is designed using a 65 nm complementary metal-oxide-semiconductor (CMOS) process with 1.2 V supply voltage. The area and power consumption of each transceiver lane are 0.136 ㎟ and 17.4 mW/GSymbol/s, respectively. The proposed channel mismatch correction reduces the time jitter of 88.6 ps caused by the channel mismatch to 34.9 ps.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.70-78
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• 2009

This paper addresses the analysis and the design optimization of differential interconnects for high-speed Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, and time-domain transient simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.6-14
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• 2011

This paper presents the design of the battery sensor IC for instrumentation of current, voltage using delta-sigma ADC. The proposed circuit consists of programmable gain instrumentation amplifier (PGIA) and second-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a 0.25 ${\mu}m$ CMOS technology. Design circuit show that the modulator achieves 82 dB signal-to-noise ratio (SNR) over a 2 kHz signal bandwidth with an oversampling ratio (OSR) of 256 and differential nonlinearity (DNL) of ${\pm}$ 0.3 LSB, integral nonlinearity (INL) of ${\pm}$ 0.5 LSB. Power consumption is 4.5 mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.8
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• pp.1825-1830
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• 2015

In some cases, despite the pedestrian jaywalking pedestrian traffic lights to red, or even wait for the walk signal to stand down in the driveway. If this is the case may be liable to lead to a traffic accident. Thus, using an infrared sensor wateuna adopted the approach that the warning announcement when a pedestrian enters the driveway, curved pedestrian crossing the intersection in this case, it is difficult to install. In this paper, we propose a Fitness referral system utilizes a built-in sensor of the Android mobile devices. For this purpose, the sensor is a proximity sensor using an acceleration sensor. The proximity sensor has a number of disadvantages compared to the high precision battery power, the acceleration sensor accuracy, fast response time, on the other hand, the disadvantage is the lower. Close to reduce battery consumption of the sensor, BMI of the user sensor control mechanism and increase the accuracy of the acceleration sensor (Body Mass Index) obtained after the index was applied to the recommendation algorithm, which like the movement mechanism.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.5
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• pp.508-514
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• 2004

A fluxgate magnetic sensor consists of a solenoid excitation coil, pick-up coil, and magnetic core. We presents the effect of magnetic core shape in a micromachined fluxgate sensor. To observe the performance of fluxgate sensor with magnetic core side width and gap, side width of 125 ${\mu}{\textrm}{m}$, 250 ${\mu}{\textrm}{m}$, and 500 ${\mu}{\textrm}{m}$ were designed in a rectangular-ring shaped core and the gaps of 0 ${\mu}{\textrm}{m}$, 50 ${\mu}{\textrm}{m}$, and 100 ${\mu}{\textrm}{m}$ were also fabricated in a racetrack shaped core. The solenoid coils and magnetic core were separated by benzocyclobutane(BCB) which had high insulation and good planarization characters. Copper coil patterns of 10 ${\mu}{\textrm}{m}$ width and 6${\mu}{\textrm}{m}$ thickness were electroplated on Ti(300 $\AA$) / Cu(1500 $\AA$) seed layers. 3 ${\mu}{\textrm}{m}$ thick N $i_{0.8}$F $e_{0.2.}$(permalloy) film for the magnetic core was also electroplated under 2000 gauss to induce the magnetic anisotropy. The magnetic core had the high DC effective permeability of ∼1,300 and coercive field of ∼0.1 Oe. Because the magnetic cores of 500 ${\mu}{\textrm}{m}$ side width and 0 gap had a low magnetic flux leakage, high sensitivity of ∼350 V/T were measured at excitation condition of 3 $V_{P-P}$ and 2 MHz square wave. The power consumption of ∼14 ㎽ was measured. The fabricated fluxgate sensor had the very small actual size of 3.0${\times}$1.7 $\textrm{mm}^2$. When two fluxgates were perpendicularly aligned in terrestrial field, their two-axis output signals were very useful to commercialize an electronic azimuth compass for the portable navigation system.m.m.m.

• Journal of Sensor Science and Technology
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• v.8 no.4
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• pp.327-332
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• 1999

Catalytic combustion type gas sensors were fabricated by using noble metal(Pt and Pd) added ${\gamma}-Al_2O_3$ powder with specific surface area of $200\;m^2/g$. The fabricated sensor showed power consumption of 500 mW at the operating voltage of 1.75 V and high sensitivity of about 120 mV for butane, methane, or propane 100%LEL, respectively. The sensor properties also showed good linearity to hydrocarbon gas concentration variation, reproductivity and stability for relative humidity variation. And it showed high stability in butane ambient for 100 days.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.159-167
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• 2005

Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.