• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.809-812
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• 2002

This paper presents the structures for a CPW shunt RF switch using MEMS(Micro Electro Mechanical System). Recent development in MEMS technology has made the design and fabrication of micro-mechanical switches as new switching elements. The micro-mechanical switches have low insertion loss, negligible power consumption, and good isolation compared to semiconductor switches. The fabricated structure shows an insertion loss of 2dB at 20GHz When a bias voltages of 12V is apply.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.368-369
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• 2006

Ferroelectric thin films have attracted much attention for applications in nonvolatile ferroelectric random access memories(NVFeRAM) from the view points of high speed operation, low power consumption, and large scale Integration[1,2]. Among the FRAM, BLT is of particular interest. as it is not only crystallized at relatively low processing temperature, but also shows highly fatigue resistance and large remanent polarization Meanwhile, these submicron ferroelectric capacitors were fabricated by a damascene process using Chemical mechanical polishing (CMP). BLT capacitors were practicable by a damascene process using CMP. The P-E hysteresis were measured under an applied bias of ${\pm}5V$ by using an RT66A measurement system. The electric properties such as I-V were determined by using HP4155A analysers.

• ETRI Journal
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• v.31 no.3
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• pp.348-350
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• 2009

To fit the limited volume and power consumption of the passive radio frequency transmission system of the electronic time fuze, an improved coded mark inversion (CMI) is proposed in this letter. From the performance analysis, the energy transmission efficiency of this encoding method is at least 50% higher than that of CMI and NRZ. Finally, the experiment results show that by adopting this improved CMI, the change of DC voltage through magnetic coupling is lower than 0.2 V when the accuracy of data transmission is above 99.5%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.128-130
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• 2000

A new type ac plasma display panels(PDPs) cells are designed and tested electrically and optically. One cells have the structure of sin discharge path shape and small electrode area. The other cells have the non-symmetric structure with a same electrode area. They show a higher luminous efficienccy and a lower power consumption about 30% improvement than the conventional standard ac PDP cells.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.541-542
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• 2008

We propose an architecture for a lighting engine for mobile 3D graphics. The proposed architecture has a variable pipeline depending on lighting effects and the number of lighting sources so that unnecessary operations and power consumption are minimized. We design a lighting engine basedon the proposed architecture using Verilog-HDL and synthesized it using a 0.25um CMOS standard cell library at 100MHz. The synthesis results show that it occupies 180,000 and 260,000 gates for 24bit and 32bit formats, respectively.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.649-650
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• 2008

In order to resolve mechanical limit in HDD, recently, the hybrid hard disk combining HDD and a flash memory was launched. In this paper, we propose a simulator for hybrid hard disk which considers redirection, flushing and spin-down function to complement the difference between HDD and hybrid hard disk. The simulator was implemented in linux kernel 2.6.20 by modifying system calls related with file system. The experiment shows that the power consumption of hybrid hard disk is 47% smaller than that of hard disk in laptop PC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.188-193
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• 2003

This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.2B no.3
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• pp.100-108
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• 2002

A simple sustain driver employing an energy recovery function is proposed as a highly efficient driver of a plasma display panel. The proposed driver uses dual resonance in the sustaining mode operation: a main resonance between an inductor and an external capacitor to produce alternative pulses and a sub-resonance between an inductor and a panel to recover the energy consumption by the capacitive displacement current of the PDP. The operational principle and design procedure of the proposed circuit are presented with theoretical analysis. The operation of the proposed sustain driver is verified through simulation and experiments based on a 7.5-inch-diagonal panel with a 200 KHz operating frequency.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2067-2070
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• 2002

In this paper, a VLSI architecture for transform and quantization module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling CIF image formats. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.