• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.435-436
• /
• 2008

This paper presents a dual band frequency synthesizer for GSM and Wideband CDMA which is designed in a standard 0.13um CMOS 1P6M process. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divider(128/129 DMP, 4bit PC, 3bit SC) and Low noise Ring-VCO. A high-speed low power dual modulus prescaler is proposed to operate up to 2.1GHz at 3.3V supply voltage with 2mW power consumption by simulation. The simulated phase noise of VCO is -101dBc/Hz at 200kHz offset frequency from 1.9GHz.

• 한국산업정보학회논문지
• /
• 제17권3호
• /
• pp.27-34
• /
• 2012

This paper presents the impact of time dependent dielectric breakdown (TDDB, also called as gate oxide breakdown) failure on nanoscale digital CMOS Circuits. Recently, TDDB for ultra-thin gate oxides has been considered as one of the critical reliability issues which can lead to performance degradation or logic failures in nanoscale CMOS devices. Also, leakage power in the standby mode can be increased significantly. In this paper, TDDB aging effects on large CMOS digital circuits in the 45nm technology are analyzed. Simulation results show that TDDB effect on MOSFET circuits can result in more significant increase of power consumption compared to delay increase.

• 전자공학회논문지C
• /
• 제35C권7호
• /
• pp.46-58
• /
• 1998

In this paper, we propose a synthesis algorithm for the design of low powe rcombinational circuits under area constraints. The proposed algorithm partitions a given circuit into several subcircuits such that only a selected subcircuit is activated at a time, hence reduce unnecessary signal transitions. Partitioning of a given circuit is performed through adaptive simulated annealing algorithm employing the cost function reflecting poer consumption under area constraints. Experimental reuslts for the MCNC benchmark circuits show that the proposed algorithm generates the circuits which consume less power by 61.1% and 51.1%, when compared to those generated by the sis 1.2 and the precomputation algorithm, respectively.

• Transactions on Electrical and Electronic Materials
• /
• 제2권2호
• /
• pp.1-4
• /
• 2001

Urgency of using plasma-energy technologies in power industry, is outlined, increasing of economical efficiency, decreasing of energy consumption and decreasing of environmental pollution, are shown, scientific and technical bases for plasma-energy technologies of fuel utilisation, are designed, results of theoretical, experimental and rig investigations of processes of plasma ignition, gasification, thermochemical preparation for burning and combined processing of coals, are presented, results of realisation of plasma technologies of residual-oil-free (mazout) pulverised-coal boiler kindling, lighting of torch and stabilisation of luid slagging in furnaces with removal of fluid slag, are described.

• 한국전기전자재료학회논문지
• /
• 제16권12S호
• /
• pp.1255-1260
• /
• 2003

In order to reduce driving power consumption, we propose and fabricate a new structure of asymmetric SOI 1${\times}$2 thermo-optic switch that has a back side silicon trenched structure. Compared to conventional SOI thermo optic switches without heat sink structure, it shows an improvement of switching power reduction from about 4 watt to 1.8 watt without sacrificing cross talk of about 20 ㏈ at the light wavelength of 1.55 $\mu\textrm{m}$. Here we also described the main design consideration and fabrication procedure for the proposed device.

• ETRI Journal
• /
• 제33권3호
• /
• pp.393-400
• /
• 2011

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 ${\mu}m$ CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 ${\mu}W$).

• 한국전기전자재료학회논문지
• /
• 제30권4호
• /
• pp.258-262
• /
• 2017

Recently energy consumption has been increasing because of advances in the industry, and electrical fires have accounted for 31.9% of all fire accidents. An electrical fire is caused by a short circuit, power surge, or poor contact. Safety devices for short circuits or power surges are currently mandatory and can actually detect problems, but arcing caused by contact failure is difficult to detect in advance. This study used an IR sensor to detect the heat concentration caused by the arc. The data from the low-resolution sensor was amplified as much as four times by interpolation to find the exact location of the heat source and were then investigated.

• 한국전자통신학회논문지
• /
• 제8권10호
• /
• pp.1545-1552
• /
• 2013

본 논문은 안드로이드를 지원하는 ARM A8-cortex 프로세서를 기반으로 임베디드 플랫폼을 구현하였다. S5PV210의 삼성 CPU를 사용함으로서 32Bit RISC 마이크로컨트롤러(ARMv7) 구조에 적합하고, 주변기기에 호환가능하며, 응용에 확장 가능하도록 설계하였다. 또한 개발한 임베디드 플랫폼은 여러 가지 기능과 높은 효율성을 제공할 뿐만 아니라, 비교적 낮은 단가와, 낮은 전력사용, 높은 성능을 제공할 수 있다.

• 센서학회지
• /
• 제30권1호
• /
• pp.15-19
• /
• 2021

Image processing is one of the major techniques that are used for computer vision. Nowadays, researchers are using machine learning and deep learning for the aforementioned task. In recent years, digit recognition tasks, i.e., automatic meter recognition approach using electric or water meters, have been studied several times. However, two major issues arise when we talk about previous studies: first, the use of the deep learning technique, which includes a large number of parameters that increase the computational cost and consume more power; and second, recent studies are limited to the detection of digits and not storing or providing detected digits to a database or mobile applications. This paper proposes a system that can detect the digital number of meter readings using a lightweight deep neural network (DNN) for low power consumption and send those digits to an Android mobile application in real-time to store them and make life easy. The proposed lightweight DNN is computationally inexpensive and exhibits accuracy similar to those of conventional DNNs.

• 한국전기전자재료학회논문지
• /
• 제35권5호
• /
• pp.452-458
• /
• 2022

The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.