• 한국CDE학회논문집
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• 제9권4호
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• pp.416-424
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• 2004

In this paper, the heat transfer analysis and thermal stress analysis of the PCB(Printed Circuit Board) equipped in electronic Packages are carried out for various may types of chips on the PCB. And two structural PCB models are used in the analyses. The electronic chips on the PCB usually emit heat and this heat generates the thermal stress around the chip. The thermal load due to the heat generation of chips on the PCB may cause the malfunction of the electronic packages such as a monitor. a computer etc. Hence, the PCB should be designed to withstand these thermal loads. In this paper, the heat transfer analysis and thermal stress analysis are executed for the PCB model with pins and the analysis results are compared with the results for the PCB model without pins. The analysis results show that the PCB model without pins is not good for the thermal stress analysis of PCB, even though these two models have similar heat transfer characteristics. The analysis results also show that the highest thermal stress occurs in the pin especially attached to the highest temperature chip, and the PCB constrained to the electronic package on the long side is structurally more stable than other cases. The analyses of the PCB are executed using the finite element analysis code, NISA.

• 마이크로전자및패키징학회지
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• 제7권1호
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• pp.61-73
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.487-488
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• 2006

In this paper, we analyzed the FBGA packages operating in high speeds and high frequency rates for DRAM. Using 3D simulations, we could extract s-parameters of packages. We realize that the proposed FBGA package does not operate properly at 3Gbps bacause the FBGA package have delta-I noise($V_{{\Delta}I-peak}$) of 132.0mV and crosstalk of 300mV, which is 25% of the operating clock level.

• 대한기계학회논문집A
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• 제33권4호
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• pp.380-387
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• 2009

The reliability concerns of solder interconnections in flip chip PBGA packages are produced mainly by the mismatch of coefficient of thermal expansion(CTE) between the module and PCB. Finite element analysis has been employed extensively to simulate thermal loading for solder joint reliability and deformation of packages in electronic packages. The objective of this paper is to study the thermo-mechanical behavior of FC-PBGA package assemblies subjected to temperature change, with an emphasis on the effect of the finite element model, material models and temperature conditions. Numerical results are compared with the experimental results by using $moir{\acute{e}}$ interferometry. Result shows that the bending displacements of the chip calculated by the finite element analysis with viscoplastic material model is in good agreement with those by $moir{\acute{e}}$ inteferometry.

• Transactions on Electrical and Electronic Materials
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• 제2권3호
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• pp.28-32
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• 2001

It was studied in the present work how the thermal cycling performance of LOC (lead on chip) packages depends on the package construct or leadframe materials. First, package body thickness and Au wire diameter were manipulated for the selection of proper package design. Secondly, two different types of leadframe materials (i.e. copper and 52%Fe-48%Ni alloy) were tested to determine the better material for improved reliability margin of plastically encapsulated microelectronic packages. This work shows that manipulating package body thickness was more effective than an increase of Au wire from 23$\mu\textrm{m}$ to 33$\mu\textrm{m}$ for the prevention of wire debonding failure. Further, this work indicates that the LOC packages including the copper leadframes can be more susceptible to thermal cycling reliability degradation due to chip cracking than those including the alloy leadframes.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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• pp.138-141
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• 2002

There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2004년도 추계학술대회 논문집
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• pp.1113-1118
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• 2004

This paper presents the dynamic analysis method for an electromechanical system. The engineer has at his disposal a variety of software simulation tools. However, difficulties arise when the study of the behavior of complex electromechanical systems in combination with coupling element is required. Typical examples of such systems are machines for factory automation, home automation, and office automation. Dynamic systems analysis packages or electronic systems analysis packages offer the restrictive to simulate these mixed systems such electromechanical product. Electronic circuit analysis algorithm is easily incorporated into a multi-body dynamics analysis algorithm. The governing equation of electronic circuit is formulated as a differential algebraic equation form including both electrical and mechanical variables and is simultaneously solved in every time step. This analysis method clearly demonstrates the application potential for mixed electromechanical simulation.

• 한국신뢰성학회지:신뢰성응용연구
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• 제16권4호
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• pp.347-355
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• 2016

Purpose: With the advance of miniaturization of electronic products, stacked packages of high density semiconductors are commonly used. Potential failure modes and mechanisms of stacked packages are identified. Methods: Failure modes and mechanisms of thin chip stacked packages are determined through the categorization and failure analysis: delamination, non-wet, crack, ESD, EMI and the process related damages. Results: Those failure modes are not easy to find and require excessive amount time and effort for analysis and subsequent improvement. Conclusion: In this study, a method of estimating the failure rate based on the strength measurement is suggested.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2005년도 추계학술대회논문집
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• pp.143-146
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• 2005

In modern automotive control modules, mechanical failures of surface mounted electronic components such as microprocessors, crystals, capacitors, transformers, inductors, and ball grid array packages, etc., are mai or roadblocks to design cycle time and product reliability. This paper presents a general methodology of failure analysis and fatigue prediction of these electronic components under automotive vibration environments. Mechanical performance of these packages is studied through finite element modeling approach fur given vibration environments in automotive application. Using the results of vibration simulation, fatigue lift is predicted based on cumulative damage analysis and material durability information. Detailed model of solder/lead joints is built to correlate the system level model and obtain solder strains/stresses. The primary focus in this paper is on surface-mount interconnect fatigue failures and the critical component selected for this analysis is 80 pin plastic leaded microprocessor.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2007년도 춘계학술발표대회 및 제12회 신소재 심포지엄
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• pp.16.2-16.2
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• 2007