• Journal of the Korean Society of Safety
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• v.39 no.2
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• pp.38-43
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• 2024

Recently, with the expanding market for electronic devices and electric vehicles, secondary battery usage has been on the rise. Lithium-ion batteries are particularly popular due to their fast charging times and lightweight nature compared to other types of batteries. A secondary battery consists of four components: anode, cathode, electrolyte, and separator. Generally, the positive and negative electrode materials of secondary batteries are composed of an active material, a binder, and a conductive material. Acetylene Black (AB) is utilized to enhance conductivity between active material particles or metal dust collectors, preventing the binder from acting as an insulator. However, when recycling waste batteries that have been subject to high usage, there is a risk of fire and explosion accidents, as accurately identifying the characteristics of Acetylene Black dust proves to be challenging. In this study, the lower explosion limit for Acetylene Black dust with an average particle size of 0.042 ㎛ was determined to be 153.64 mg/L using a Hartmann-type dust explosion device. Notably, the dust did not explode at values below 168 mg, rendering the lower explosion limit calculation unfeasible. Analysis of explosion delay times with varying electrode gaps revealed the shortest delay time at 3 mm, with a noticeable increase in delay times for gaps of 4 mm or greater. The findings offer fundamental data for fire and explosion prevention measures in Acetylene Black waste recycling processes via a predictive model for lower explosion limits and ignition delay time.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.3
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• pp.166-175
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• 2024

In this paper, the Window-Masking Method and HAT (Hardware Attached Top) CPU SoM (System on Module) are used to improve the performance and reduce the weight of the MANET (Mobile Ad-hoc Network) network synchronization system using time division redundancy. We propose converting it into a RISC-V based soft-core MCU and mounting it on an FPGA, a hardware accelerator. It was also verified through experiment. In terms of performance, by applying the proposed technique, the synchronization acquisition range is from -50dBm to +10dBm to -60dBm to +10dBm, the lowest input level for synchronization is increased by 20% from -50dBm to -60dBm, and the detection delay (Latency) is 220ns. Reduced by 43% to 125ns. In terms of weight reduction, computing resources (48%), size (33%), and weight (27%) were reduced by an average of 36% by replacing with soft-core MCU.

• Journal of Cardiovascular Imaging
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• v.30 no.1
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• pp.62-75
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• 2022

BACKGROUND: Due to its location very close to the bundle of His, mitral annulus calcification (MAC) might be associated with the development of atrioventricular (AV) conduction disturbances. This study assessed the association between MAC and AV conduction disturbances identified by cardiac implantable electronic device (CIED) use and electrocardiographic parameters. The association between MAC and traditional cardiovascular risk factors was also assessed. METHODS: This cross-sectional study analyzed 14,771 participants, predominantly men aged 60-75 years, from the population-based Danish Cardiovascular Screening trial. Traditional cardiovascular risk factors were obtained. Using cardiac non-contrast computed tomography imaging, MAC scores were measured using the Agatston method and divided into absent versus present and score categories. CIED implantation data were obtained from the Danish Pacemaker and Implantable Cardioverter Defibrillator Register. A 12-lead electrocardiogram was available for 2,107 participants. Associations between MAC scores and AV conduction disturbances were assessed using multivariate regression analyses. RESULTS: MAC was present in 22.4% of the study subjects. Participants with pacemakers for an AV conduction disturbance had significantly higher MAC scores (odds ratio [OR], 1.11; 95% confidence interval [CI], 1.01-1.23) than participants without a CIED, whereas participants with a CIED for other reasons did not. Prolonged QRS-interval was significantly associated with the presence of MAC (OR, 1.45; 95% CI, 1.04-2.04), whereas prolonged PQ-interval was not. Female sex and most traditional cardiovascular risk factors were significantly associated with high MAC scores. CONCLUSIONS: MAC was associated with AV conduction disturbances, which could improve our understanding of the development of AV conduction disturbances.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.4
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• pp.213-220
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• 2024

This paper proposes an optimization strategy for performing Federated Learning between devices and edge clouds using WebAssembly (WASM). The proposed strategy aims to maximize efficiency by conducting partial training on devices and the remaining training on edge clouds. Specifically, it mathematically describes and evaluates methods to optimize data transfer between GPU memory segments and the overlapping of computational tasks to reduce overall training time and improve GPU utilization. Through various experimental scenarios, we confirmed that asynchronous data transfer and task overlap significantly reduce training time, enhance GPU utilization, and improve model accuracy. In scenarios where all optimization techniques were applied, training time was reduced by 47%, GPU utilization improved to 91.2%, and model accuracy increased to 89.5%. These results demonstrate that asynchronous data transfer and task overlap effectively reduce GPU idle time and alleviate bottlenecks. This study is expected to contribute to the performance optimization of Federated Learning systems in the future.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.12
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• pp.126-134
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• 2017

There have been numerous studies on extracting the R-peak from electrocardiogram (ECG) signals. However, most of the detection methods are complicated to implement in a real-time portable electrocardiograph device and have the disadvantage of requiring a large amount of calculations. R-peak detection requires pre-processing and post-processing related to baseline drift and the removal of noise from the commercial power supply for ECG data. An adaptive filter technique is widely used for R-peak detection, but the R-peak value cannot be detected when the input is lower than a threshold value. Moreover, there is a problem in detecting the P-peak and T-peak values due to the derivation of an erroneous threshold value as a result of noise. We propose a robust R-peak detection algorithm with low complexity and simple computation to solve these problems. The proposed scheme removes the baseline drift in ECG signals using an adaptive filter to solve the problems involved in threshold extraction. We also propose a technique to extract the appropriate threshold value automatically using the minimum and maximum values of the filtered ECG signal. To detect the R-peak from the ECG signal, we propose a threshold neighborhood search technique. Through experiments, we confirmed the improvement of the R-peak detection accuracy of the proposed method and achieved a detection speed that is suitable for a mobile system by reducing the amount of calculation. The experimental results show that the heart rate detection accuracy and sensitivity were very high (about 100%).

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• The Journal of Korean Society for Radiation Therapy
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• v.26 no.2
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• pp.297-303
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• 2014

Purpose : The purpose of this study is reproducibility evaluation of deep inspiration breath-hold(DIBH) technique by respiration data and heart position analysis in radiation therapy for Left Breast cancer patients. Materials and Methods : Free breathing(FB) Computed Tomography(CT) images and DIBH CT images of three left breast cancer patients were used to evaluate the heart volume and dose during treatment planing system( Eclipse version 10.0, Varian, USA ). The signal of RPM (Real-time Position Management) Respiratory Gating System (version 1.7.5, Varian, USA) was used to evaluate respiration stability of DIBH during breast radiation therapy. The images for measurement of heart position were acquired by the Electronic portal imaging device(EPID) cine acquisition mode. The distance of heart at the three measuring points(A, B, C) on each image was measured by Offline Review (ARIA 10, Varian, USA). Results : Significant differences were found between the FB and DIBH plans for mean heart dose (6.82 vs. 1.91 Gy), heart $V_{30}$ (68.57 vs. $8.26cm^3$), $V_{20}$ (76.43 vs. $11.34cm^3$). The standard deviation of DIBH signal of each patient was ${\pm}0.07cm$, ${\pm}0.04cm$, ${\pm}0.13cm$, respectively. The Maximum and Minimum heart distance on EPID images were measured as 0.32 cm and 0.00 cm. Conclusion : Consequently, using the DIBH technique with radiation therapy for left breast cancer patients is very useful to establish the treatment plan and to reduce the heart dose. In addition, it is beneficial to using the Cine acquisition mode of EPID for the reproducibility evaluation of DIBH.

• The Journal of Korean Society for Radiation Therapy
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• v.29 no.2
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• pp.65-73
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• 2017

Purpose: Machine Performance Check (MPC) is a self-checking software based on the Electronic Portal Imaging Device (EPID) to measure daily beam outputs without external installation. The purpose of this study is to verify the usefulness of MPC by comparing and correlating daily beam output of QA Beamchecker PLUS. Materials and Methods: Linear accelerator (Truebeam 2.5) was used to measure 10 energies which are composed of photon beams(6, 10, 15 MV and 6, 10 MV-FFF) and electron beams(6, 9, 12, 16 and 20 MeV). A total of 80 cycles of data was obtained by measuring beam output measurement before treatment over five months period. The Pearson correlation coefficient was used to evaluate the consistency of the beam output between the MPC and the QA Beamchecker PLUS. In this study, if the Pearson correlation coefficient is; (1) 0.8 or higher, the correlation is very strong (2) between 0.6 and 0.79, the correlation is strong (3) between 0.4 and 0.59, the correlation is moderate (4) between 0.2 and 0.39, the correlation is weak (5) lower than 0.2, the correlation is very weak. Results: Output variations observed between MPC and QA Beamchecker PLUS were within 2 % for photons and electrons. The beam outputs variations of MPC were $0.29{\pm}0.26%$ and $0.30{\pm}0.26%$ for photon and electron beams, respectively. QA Beamchecker PLUS beam outputs were $0.31{\pm}0.24%$ and $0.33{\pm}0.24%$ for photon and electron beams, respectively. The Pearson correlation coefficient between MPC and QA Beamchecker PLUS indicated that photon beams were very strong at 15 MV, and strong at 6 MV, 10 MV, 6 MV-FFF and 10 MV-FFF. For electron beams, the Pearson correlation coefficient were strong at 16 MeV and 20 MeV, moderate at 9 MeV and 12 MeV, and very weak at 6 MeV. Conclusion: MPC showed significantly strong correlation with QA Beamchecker PLUS when testing with photon beams and high-energy electron beams in the evaluation of daily beam output, but the correlation when testing with low-energy electron beams (6 MeV) appeared to be low. However, MPC and QA Beamchecker PLUS are considered to be suitable for checking daily beam output, as they performed within 2 % of beam output consistency during the observation. MPC which can perform faster than the conventional daily beam output measurement tool, is considered to be an effective method for users.