• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.33-41
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• 2000

Pyroelectric characteristics such as voltage responsivity, noise equivalent power and detectivity are modeled 3-dimensionaly considering th interaction of each parameters. Also, the circuit is designed to set up the frequency band width and the signal amplification of the pyroelectric IR sensor. The case of low frequency region shows that the voltage response increases with the independence of the sensor area as the thickness decreases. In the high frequency region, it is found that the voltage response with the load resistor of 20$G{\Omega}$ increases with the independence of the sensor thickness as the sensor area decreases. In the low frequency region, the detectivity becomes excellent at th load resistor of 20$G{\Omega}$, the sensor area larger than $4{\times}10^{-10}m^2$ and the sensor thickness thinner than $1{\times}10^{-5}m$, while, in the high frequency region, it shows high value at the sensor thickness thinner than $1{\times}10^{-5}m$ and the sensor area smaller than $2{\times}10^{-10}m^2$ with the independence of the load resistor. In the circuit design, quasi-boot-strap circuit is employed, in which a single op-amp is connected to the drain of JFFT. Desirable frequency band width, amplification rate and the remarkable drop of noise of about 56% from that of conventional circuits with double op-amps are obtained.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• The KIPS Transactions:PartA
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• v.19A no.1
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• pp.51-60
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• 2012

IC(Integrated circuits)card, generally be named smard card, embedded MPU(Micro Processor Unit) of small-size, memory, EEPROM, Card Operating System(COS) and security algorithm. The IC card is used in almost all industry such as a finance(credit, bank, stock etc.), a traffic, a communication, a medical, a electronic passport, a membership management and etc. Recently, a application field of IC card is on the increase by method for payments of T-commerce, as T-commerce is becoming a new growth engine of the broadcating industry by trend of broadcasting and telecommunication convergence, smart mechanization of TV. For example, we can pay in IC credit card(or IC cash card) on T-Commerce. or we can be provided TV banking service in IC cash card such as ATM. However, so far, T-commerce payment services have weakness in security such as storage and disclosure of card information as well as dropping sharply about custom ease because of taking advantage of card information input method using remote control. To solve this problem, This paper developed processing payment module for implementing TV electronic payment system using IC credit card payment standard, EMV.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.2
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• pp.107-115
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• 2015

In this paper, a small-area 32-bit differential paired eFuse OTP memory for power ICs is designed. In case of smaller number of rows than that of columns for the OTP memory cell array, a scheme for the cell array reducing the number of SL driver circuits requiring their larger layout areas by routing the SL (source line) lines supplying programming currents for eFuse links in the row direction instead of the column direction as well as a core circuit is proposed. In addition, to solve a failure of being blown for non-blown eFuse links by the electro-migration phenomenon, a regulated voltage of V2V ($=2V{\pm}0.2V$) is used to a RWL (read word line) driver circuit and a BL (bit line) pull-up driver circuit. The layout size of the designed 32-bit eFuse OTP memory is $228.525{\mu}m{\times}105.435{\mu}m$, which is confirmed to be 20.7% smaller than that of the counterpart using the conventional cell array routing, namely $197.485{\mu}m{\times}153.715{\mu}m$.

• Journal of Advanced Navigation Technology
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• v.22 no.6
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• pp.642-647
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• 2018

In this paper, an unequal power divider based on adjusting electrical length of uniform transmission line is presented. This divider consists of three uniform transmission lines and one isolation resistor and have the different port impedances of input and output. The feature of proposed divider can changed the power dividing ratio to adjust only electrical length of uniform transmission lines. To verify the feasibility of proposed power divider, two divider circuits are designed, one is 1:2 power dividing ratio divider with $60{\Omega}$ uniform transmission line and $40{\Omega}$ input port impedances and $45{\Omega}$ output port impedances, the performance data were measured the insertion losses of 1.7 dB/ 5.0 dB, return losses of more than -30 dB and isolation of more than -35 dB. The other is 1:4 power dividing ratio divider with $40{\Omega}$ uniform transmission line and $50{\Omega}$ input port impedances and $75{\Omega}$ output port impedances, the performance data were measured the insertion losses of 1.3 dB/ 6.8 dB, return losses of more than -12 dB and isolation of more than -19 dB. The measured performance data agreed well with the simulated results.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.3
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• pp.219-232
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• 2013

This paper presents a microstrip antenna which recovers its resonant frequency and impedance shifted automatically by the approach of other objects such as hands. This can be used for telemetry sensor applications in the ultrahigh frequency(UHF) industrial, scientific, and medical(ISM) band. It is the key element that an frequency-reconfigurable antenna could be electrically controlled. This antenna is miniaturized by loading the folded plates at both radiating edges, and varactor diodes are installed between the radiating edges and the ground plane to control the resonant frequency by adjusting the DC bias asymmetrically. Using this voltage-controlled antenna and the micro controller peripheral circuits of reading the returned level, the antenna is designed and fabricated which recovers its resonant frequency and impedance automatically. Designed frequency auto recovering antenna is conformed to be recovered within a few seconds when the resonant frequency and impedance are shifted by the approach of other objects such as hand, metal plate, dielectric and so on.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.79-84
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• 2016

A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.

• Journal of the Korean Ceramic Society
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• v.49 no.5
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• pp.475-483
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• 2012

High capacitance X5R MLCCs based on $BaTiO_3$ ceramic dielectric layers exhibit a single broad, asymmetric arc shape impedance and modulus response over the wide frequency range between 1 MHz to 0.01 Hz. Analysis according to the conventional brick-layer model for polycrystalline conductors employing a series connection of multiple RC parallel circuits leads to parameters associated with large errors and of little physical significance. A new parametric impedance model is shown to satisfactorily describe the experimental spectra, which is a parallel network of one resistor R representing the DC conductivity thermally activated by 1.32 eV, one ideal capacitor C exactly representing bulk capacitance, and a constant phase element (CPE) Q with complex capacitance $A(i{\omega})^{{\alpha}-1}$ with ${\alpha}$ close to 2/3 and A thermally activated by 0.45 eV or ca. 1/3 of activation energy of DC conductivity. The feature strongly indicate the CK1 model by J. R. Macdonald, where the CPE with 2/3 power-law exponent represents the polarization effects originating from mobile charge carriers. The CPE term is suggested to be directly related to the trapping of the electronic charge carriers and indirectly related to the ionic defects responsible for the insulation resistance degradation.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.12
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• pp.17-26
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• 1998

Ultrasonic sensors are widely used in various applications due to advantages of low cost, simplicity in construction, mechanical robustness, and little environmental restriction in usage. But for the application of object recognition, ultrasonic sensors exhibit several shortcomings of poor directionality which results in low spatial resolution of objects, and specularity which gives frequent erroneous range readings. The time-of-flight(TOF) method generally used for distance measurement can not distinguish small object patterns of plane, corner or edge. To resolve the problem, an increased number of the sensors in the forms of a linear array or 2-dimensional array of the sensors has been used. Also better resolution has been obtained by shifting the array in several steps using mechanical actuators. Also simple patterns are classified based on analyzing signal reflections. In this paper we propose a method of a sensor array system with improved capability in pattern distinction using electronic circuits accompanying the sensor array, and intelligent algorithm based on neuro-fuzzy processing of data fusion. The circuit changes transmitter output voltages of array elements in several steps. A set of different return signals from neighborhood sensors is manipulated to provide enhanced pattern recognition in the aspects of inclination angle, size and shift as well as distance of objects. The results show improved resolution of the measurements for smaller targets.