• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.112-118
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• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.657-663
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• 2016

In this work, a novel silicon (Si) based floating body synaptic transistor (SFST) is studied to mimic the transition from short-term memory to long-term one in the biological system. The structure of the proposed SFST is based on an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with floating body and charge storage layer which provide the functions of short- and long-term memories, respectively. It has very similar characteristics with those of the biological memory system in the sense that the transition between short- and long-term memories is performed by the repetitive learning. Spike timing-dependent plasticity (STDP) characteristics are closely investigated for the SFST device. It has been found from the simulation results that the connectivity between pre- and post-synaptic neurons has strong dependence on the relative spike timing among electrical signals. In addition, the neuromorphic system having direct connection between the SFST devices and neuron circuits are designed.

• Journal of The Korean Association For Science Education
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• v.24 no.3
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• pp.612-620
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• 2004

The purpose of this study was to investigate how middle and high school students represent circuit diagrams with different shapes but electrically same. What prototypes of circuit which students possessed were, how students represented the connection of resistors, and what criteria used while grouping the circuit diagrams were investigated. The participants were 10 middle and 10 high school students. The results show that they represented the circuit diagrams by the geometrical resistor configurations rather than physics principles, not considering the presence of a junction or a battery on the branch. This representation was constrained by the circuit prototypes. Middle and High school students seems to have the own way of representing circuit diagrams without considering physics principles.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.668-670
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• 2011

The Next-generation IT technology has been evolving from single technique to another which has merged, converging characteristics. The government categorized the 5 essential technologies to secure competitiveness in designing system semiconductors as smart motor vehicle info-tainment platform, smart TV multimedia system, smart phone analog interface technique, smart convergence digital communication and RF techniques, and advanced power management for smart devices. Also, it designated smart phone, smart TV, smart motor vehicle, and smart pad as the key industries. Such core techniques will become the key technologies of semiconductor design to secure the competitiveness of the next generation smart devices and the techniques can be transferred to fab-less design companies. In this contribution, we analyze the issues and the problems of the smart phone analog and interface techniques.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.91-103
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• 2015

This paper presents "The 3-User NOR switching channel based on interference decoding with receiver cooperation" in succession to "Jeju Jong Nang channel code I, II". The Jeju Jong Nang code is considered as one of the earliest human binary coded communication (HBCC) in the world with a definite "1" or "0" binary symbolic analysis of switching circuits. In this paper, we introduce a practical example of interference decoding with receiver cooperation based on the three user Jong Nang NOR switching channel. The proposed system models are the three user Jong Nang (TUJN) NOR logic switching on-off, three-user injective deterministic NOR switching channel and Gaussian interference channel (GIC) with receiver cooperation. Therefore, this model is well matched to Shannon binary symmetric and erasure channel capacity. We show the applications of three-user Gaussian interference decoding to obtain deterministic channels which means each receiver cooperation helps to adjacent others in order to increase degree of freedom. Thus, the optimal sum rate of interference mitigation through adjacent receiver cooperation achieves 7 bits.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.7-11
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• 2013

As thermosonic ball bonding is developed for more and more advanced applications in the electronic packaging industry, the control of process stresses induced on the integrated circuits becomes more important. If Cu bonding wire is used instead of Au wire, larger ultrasonic levels are common during bonding. For advanced microchips the use of Cu based wire is risky because the ultrasonic stresses can cause chip damage. This risk needs to be managed by e.g. the use of ultrasound during the impact stage of the ball on the pad ("pre-bleed") as it can reduce the strain hardening effect, which leads to a softer deformed ball that can be bonded with less ultrasound. To find the best profiles of ultrasound during impact, a numerical model is reported for ultrasonic bonding with capillary dynamics combined with a geometrical model describing ball deformation based on volume conservation and stress balance. This leads to an efficient procedure of ball bond modelling bypassing plasticity and contact pairs. The ultrasonic force and average stress at the bond zone are extracted from the numerical experiments for a $50{\mu}m$ diameter free air ball deformed by a capillary with a hole diameter of $35{\mu}m$ at the tip, a chamfer diameter of $51{\mu}m$, a chamfer angle of $90^{\circ}$, and a face angle of $1^{\circ}$. An upper limit of the ultrasonic amplitude during impact is derived below which the ultrasonic shear stress at the interface is not higher than 120 MPa, which can be recommended for low stress bonding.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.39-44
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• 2003

As the portable electronic equipments are developed and popularized, the batteies are more important. To prolong life of the equipments, engineers demand to have batteries of high-power density and they are used to use Li-ion batteries popularly Li-ion batteries are better than conventional batteries, Ni-cd, about power density per volume and weight, but they have a fault that discharge voltage of them goes down. In order to maximize life of the Li-ion batterries, we have to use a converter which is suitable for the characteristic of Li-ion batteries. Therefore, capacitive idling SEPIC(Single Ended Primary Inductance Converter) that is derived from the SEPIC topology is proposed as a source of the Portable low-power applications. The converter has characteristics of buck-boost porformance. Besides, that makes it possible to increase the switching frequency by partial soft commutation of power switches through adding a diode and a switch. This paper is presented the characteristics, DC voltage conversion ratio, circuits of operation modes, of the converter and it is analized and implemented.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.27-32
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• 1999

Metal-ferroelectric-semiconductor devices by susing rapid thermal annealed $LiNbO_3/Si$(100) structures were fabricated and demonstrated nonvolatile memory operations. The estimated field-effect electron mobility and transconductance on a linear region of the fabricated FET were about $600cm^2/V{\cdot}s$ and 0.16mS/mm, respectively. The ID-VG characteristics of MFSFET's showed a hysteresis loop due to the ferroelectric nature of the $LiNbO_3 films. The drain current of the on state was more than 4 orders of magnitude larger than the off state current at the same read gate voltage of 0.5V, which means the memory operation of the MFSFET. A write voltage as low as ${\pm}3V$, which is applicable to low power integrated circuits, was used for polarization reversal. The ferroelectric capacitors showed no polarization degradation up to $10^{10}$ switching cycles with the application of symmetric bipolar voltage pulse (peak-to-peak 6V, 50% duty cycle) of 500kHz.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.14 no.3
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• pp.15-20
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• 2015

After the US government declared 3D printing technology a next-generation manufacturing technology, there have been many practical studies conducted to expand 3D printing technology to manufacturing technologies, called AMERICA MAKES. In particular, the Keck Center, located at the University of Texas at El Paso, has studied techniques for easily combing the 3D stacking process with space mobility and expanded these techniques to simultaneous staking techniques for multiple materials. Additionally, it developed convergence manufacturing techniques, such as direct inking techniques, in order to produce a module structure that combines electronic circuits and components, such as CUBESET. However, in these studies, it is impossible to develop a unified system using traditional independent through simple sequencing connections. This is because there are many problems in the integration between the stacking modeling of 3D printers and post-machining, such as thermal deformations, the precision accuracy of 3D printers, and independently driven coordinate problems among process systems. Therefore, in this paper, the integration method is suggested, which combines these 3D printers and subsequent machining process systems through an Internet-based cloud. Additionally, the sequential integrated system of a 3D printer, an NC milling machine, machine vision, and direct inking are realized.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.1-10
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• 1998

The advent of deep submicron technologies in the age of portable electronic systems creates a moving target for CAB algorithms, which now need to reduce power as well as delay and area in the existing design methodology. This paper presents a resynthesis algorithm for logic decomposition on mapped circuits. The existing algorithm uses a Huffman encoding, but does not consider glitches and effects on logic depth. The proposed algorithm is to generalize the Huffman encoding algorithm to minimize the switching activity of non-critical subcircuits and to preserve a given logic depth. We show how to obtain a transition-optimum binary tree decomposition for AND tree with zero gate delay. The algorithm is tested using SIS (logic synthesizer) and Level-Map (LUT-based FPGA lower power technology mapper) and shows 58%, 8% reductions on power consumptions, respectively.