• Journal of Arbitration Studies
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• v.28 no.4
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• pp.89-110
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• 2018

The purposes of this study are as follows: First, this study reviews the Online Dispute Resolution (ODR) regulations of the EU to resolve disputes which can arise in international e-commerce in the future. Second, this study tries to seek out alternative solutions to dispute resolutions based on these regulations. Third, this study increases the efficiency of the transactions by proposing effective and satisfactory dispute resolution methods for international e-commerce. First, this study reviews the concept of cross-border e-commerce, generally explores ODR, and creates comparisons with Alternative Dispute Resolution (ADR). Subsequently, this study looks into domestic ODR system and analyzes the regulations of EU ODR. This study suggests the implications of the European ODR regulations in the conclusion. The EU ODR platform is considered greatly significant in that it has increased the possibility of settlements in small disputes by enhancing consumers' accessibility to ADR procedures. Therefore, this thesis proposes a method for Korean companies to resolve disputes that may arise in e-commerce with EU by using the ODR platform. As a result, it is expected to increase the competitiveness of Korean companies in the EU market. Both legislative trends related to the ODR of the EU and establishment of the EU ODR platform have significant implications for Korean businesses in Europe. This study is expected to be useful for our businesses in the EU in reviewing the applicability of the EU ODR regulations and the dispute settlement procedures through the EU ODR platform. In addition, this study is expected to prove useful in relation to consumer protection by enhancing consumers' accessibility to dispute settlement institutions in domestic electronic commerce.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10a
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• pp.770-775
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• 1987

In this paper, design and development experiences of a vision based robotic assembly system for electronic components are described. Specifically, the overall system consists of the following three subsystems each of which employs a 16 bit Preprocessor MC 68000 : supervisory controller, real-time vision system, and servo system. The three microprocessors are interconnected using the time shared common memory bus structure with hardwired bus arbitration scheme and operated as a master-slave type in which each slave is functionally fixed in view of software. With this system architecture, the followings are developed and implemented in this research; (i) the system programming language, called 'CLRC', for man-machine interface including the robot motion and vision primitives, (ii) real-time vision system using hardwired chain coder, (iii) the high-precision servo techniques for high speed de motors and high speed stepping motors. The proposed control system were implemented and tested in real-time successfully.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.04a
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• pp.164-167
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• 2004

In the paper is proposed a hierarchical adaptive fuzzy controller for balancing and position control of the inverted pendulum system. Because balancing control rules of the pendulum and position control rules of the cart can be opposite, it is difficult to design an adaptive fuzzy controller that satisfy both objectives. To stabilize the pendulum at a specified position, the hierarchical adaptive fuzzy controller consists of a robust indirect adaptive fuzzy controller for balancing, a forced disturbance generator which emulates heuristic control strategy, and a supervisory decision maker for the arbitration of two control objectives It is proved that all the signals in the overall system are bounded. Simulation results are given to verify the proposed adapt i ye fuzzy control method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.33-39
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• 2011

H.264 decoders usually have pipeline architecture by a macroblock or a 4 ${\times}$ 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. Adaptive pipeline architecture for H.264 decoders has been proposed for efficient decoding and lower the requirement of the bandwidth for the memory bus. However, it requires a controller for the adaptive priority control to utilize the advantage. We propose a smart bus arbiter that replaces the controller. It is introduced to adjust the priority adaptively the QoS (Quality of Service) control of the decoding process. The smart arbiter can be integrated the arbiter of bus systems and it works when certain conditions are met so that it does not affect the original functions of the arbiter. An H.264 decoder using the proposed architecture is designed and implemented to verify the operation using an FPGA.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2628-2645
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• 2017

This paper proposes a new offline electronic payment (e-payment) system that satisfies the major security requirements of e-payment, i.e. anonymity, unlinkability, unforgeability, double spending control, conditional traceability, and fraud prevention. The central idea is the use of Hwang et al.'s RSA-based untraceable blind signature (BS), which disables the link between the e-coin and its owner and ensures the anonymity of both the customer and the merchant. It attaches an expiration, a deposit and the transaction dates to each e-coin in order to manage the database of the bank effectively, to correctly calculate the interest on the e-coin and to aid arbitration if a dishonest customer attempts to double-spend the coin. It also ensures the anonymity of the customer as long as the coin is spent legitimately. Only when a fraudulent e-coin transaction is detected can the bank, with the help of the central authority (a trusted entity), determine the identity of the dishonest customer. The system is referred to as offline since the bank does not need to be concurrently involved in transactions between a customer and a merchant. Finally, analyses of the performance of the prototype and the primary security requirements of the proposed system are also presented.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.11
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• pp.1083-1092
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• 2016

In this paper, the performance of the optical code-division multiple access (OCDMA) technology on a plastic optical fiber (POF) access network, which had received much attention due to its low weight, large core diameter, flexibility, easy installation, and especially its high bandwidth, is analyzed. Recently, POF was a very attractive candidate for transmission media in an access network based on OCDMA technology. But the conventional OCDMA system only allows finite units to transmit and access simultaneously according to the number of channels which are restricted by BER, and so, in this paper, to resolve this problem a novel multi-priority reservation protocol is also proposed. By using this reservation scheme and a distributed arbitration algorithm, channel collision and destination conflict could be avoided. And this protocol can efficiently support the transmission of multimedia messages that require the different time-delay. The network throughput and average delay using various system parameters have been investigated by numerical analysis and simulation experiments. These results shows that the multi-priority reservation protocol in this POF access network based on OCDMA technology is valid and efficient.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.3
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• pp.213-219
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• 2017

Recently, the Internet Protocol Television (IPTV) services have become very common, enabling various Internet-based services as well as watching TV. In the IPTV system, a Set-Top box (STB) plays a key role as a network terminal device that transmits and receives realtime multimedia contents. In addition, the IPTV networks are usually supported by broadband optical fiber-base network such as fiber-to-the-home (FTTH), However, a general IPTV STB is regarded as one of the local area network (LAN)-attached devices while sharing the bandwidth of the LAN (e.g., Ethernet). In order to overcome the limited bandwidth utilization by fully facilitating the broadband bandwidth (e.g., 1 Gbps) of the optical fiber-based network, we propose a new FC (Fiber Channel)-embedded IPTV STB which can be directly attached to the optical fiber network. Then, we verify that the impacts of the proposed FC-embedded IPTV STB by organizing the the FC-AL (Fiber Channel-Arbitration Loop) network equipped with the FC-embedded IPTV We measures the average Start-up Delay, Average Reject Ratio and the Number of Concurrent Users through extensive simulations to investigate the performances of the suggested FC-AL-based IPTV network. Surprisingly, the IPTV network architecture with the proposed FC-embedded IPTV STBs has an excellent average start-up delay of less than 10 msec, an acceptable average reject ratio of less than 3 % as well as a linear increase of the number of concurrent users when extending the architecture. This reveals that the proposed FC embedded STB has a superior impacts on the performance of the entire IPTV network by effectively utilizing the broadband bandwidth of the fiber optic-based network.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.68-75
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• 2011

The performance of peripheral devices is improving rapidly to meet the needs of users for multimedia data. Therefore, the peripheral interface with wide bandwidth and high transmission rate becomes necessary to handle large amounts of data in real time for multiple high-performance devices. PCI Express is a fast serial interface with the use of packets that are compatible with previous PCI and PCI-X. In this paper, we design and verify general peripheral interface using serial link. It includes two kinds of traffic class (TC) labels which are mapped to virtual channels (VC). The design adopts TC/VC mapping and the scheme of arbitration by priority. The design uses a packet which can be transmitted through up to four transmission lanes. The design of general peripheral interface is described in Verilog HDL and verified using ModelSim. For FPGA verification, Xilinx ISE and SPARTAN XC3S400 are used.We used Synopsys Design Compiler as a synthesis tool and the used library was MagnaChip 0.35um technology.