• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.983-986
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• 2005

This paper describes a digital convergence platform(DCP) whice is implemented based on the MPEG-21 multimedia framework. The DCP is a newly proposed solution in this research for the convergence service of future home multimedia environment. The DCP is a common platform designed to have the feature of configurability, via means of S/W, which is needed for the convergence service of diverse digital media. A distributed peer to peer service and transaction model is also a new feature realized in the DCP using the MPEG-21 multimedia framework. A prototype DCP is implemented to verify its functions of multimedia service and transactions. The developed DCPs are networked with IP clustering storage systems for the distributed service of multimedia. Successful streaming services of the MPEG-2/4 video and audio are verified with the implemented test-bed system of the DCP.

• ETRI Journal
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• v.34 no.1
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• pp.44-54
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• 2012

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.65-68
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• 2003

3GPP's RLC protocol specification adopted an error control scheme based on selective repeat ARQ. In 3GPP ARQ, distinctive windows are provide at transmitting and receiving stations so that those stations are prohibited to send or receive data PDU's out of window. An increase in window size enhances delay performance. Such an increase, however, raises the occupancy at reordering buffer, which results in a long reordering time. Aiming at suppressing the occupancy at reordering buffer, we propose a occupancy control scheme in this paper. In this scheme, a threshold is created in the receiving station's window and a data PDU out of the threshold (but within the window) is treated according to go back N ARQ. By the employment of the occupancy control scheme, the occupancy at the reordering buffer is apparently reduced, while the delay performance may be degraded due to the properties of go back N ARQ. We, thus, investigate the peak occupancy and mean delay performance by a simulation method. From numerical examples, we observe a trade-off in both performance measures and conclude that the peak occupancy is effectively reduced by setting a proper threshold under a constraint on mean delay performance.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1606-1609
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• 2002

MAC state models appeared with an effort to overcome technical demerits of CDMA in provisioning packet data service. In the scenario of sojourn and transition on MAC states, the design of state sojourn time is a critical issue for an efficient utilization of limited recource; a longer sojourn time leads to more resource being preserved for inactive stations, while more connection components should be recovered with a shorter sojourn time. Thus, the sojourn time at each MAC state must be optimized in consideration of these two conflicting arguments. In this paper, we first present a generic MAC state model. Secondly, based on the generic model, we reveal a relation of inactive period and the delay time of the last packet served in pre- ceding active period and specify a loss function reflect-ing two antinomic features that result from a change of state sojourn time. Using the proposed loss function, we construct a decision problem to find an optima3 rule for state sojourn times. Finally, we present a way of computing Bayes rule by use of the posterior distribution of inactivity duration for given observation on the delay time of last packet. Furthermore, Bayes rules are explicitly expressed for special arrival processes and investigated with respect to traffic load and loss parameters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.39-46
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• 2005

A DC-DC converter with digital controller is realized. the digital controller has several advantages such as robustness, fast design time, and high flexibility. however, since the DC-DC output voltage is analog, an analog-to-digital conversion scheme is always essential in all digital controllers. A simple and efficient delta-sigma modulator is used as a conversion scheme in out implementation. The measurement results show good voltage regulation

• Journal of IKEEE
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• v.19 no.2
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• pp.260-264
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• 2015

In this paper, we propose mode selector for operating a switching system and regulator of linear system to detect the load current. The proposed mode selector can be a mode switching of linear system and switching system, and it has been proposed to compensate for the disadvantages of regulator of switching system with low efficiency in light load conditions. At light load conditions, the mode selector is possible to provide a high efficiency in light load condition by switching the mode to the regulator of linear system. The mode selector was designed to using a Dongbu Hitek $0.18{\mu}m$ CMOS process.

• Journal of IKEEE
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• v.25 no.1
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• pp.168-173
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• 2021

In this paper, we propose a new structure of ESD protection device that achieves improved electrical characteristics through structural change of LVTSCR, which is a general ESD protection device. In addition, it applies N-Stack technology for optimized design in the ESD Design Window according to the required voltage application. The N-Well area additionally inserted in the existing LVTSCR structure provides an additional ESD discharge path by electrically connecting to the anode, which improves on-resistance and temperature characteristics. In addition, the short trigger path has a lower trigger voltage than the existing LVTSCR, so it has excellent snapback characteristics. In addition, Synopsys' T-CAD Simulator was used to verify the electrical characteristics of the proposed ESD protection device.

• Journal of Electrical Engineering and Technology
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• v.9 no.4
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• pp.1355-1359
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• 2014

In the proposed work a 2D analytical modeling of single halo Triple material Surrounding Gate (SH-TMSG) MOSFET is developed. The Surface potential and Electric Field has been derived using parabolic approximation method and the simulation results are analyzed. The essential substantive is provided which elicits the deterioration of short channel effects and the results of the analytical model are delineated and compared with MEDICI simulation results and it is well corroborated.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1011-1014
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• 2005

In this paper, we propose a method that extracts an invariant biometric key in order to apply this biometric key to the crypto-biometric system. This system is a new authentication architecture which can improve the security of current cryptographic system and solve the problem of stored template protection in conventional biometric system, also. To use biometric information as a cryptographic key in crypto-biometric system, same key should be generated from the same person. However, it is difficult to obtain such an invariant biometric key because biometric data is sensitive to surrounding environments. The proposed method solves this problem by clustering Iris Codes obtained by using independent component analysis (ICA).

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.227-231
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• 2001

A new primary-side-assisted zero-voltage and zero-current switching (ZVZCS) three-level DC-DC converter with flying capacitor is proposed. The three-level converters are promising in high voltage applications, and ZVZCS is a very effective means for reducing switching losses. The proposed DC-DC converter uses only one auxiliary transformer and two diodes to obtain ZCS for the inner leg. It has a simple and robust structure, and offers soft-switching capability even in short-switching conditions. The proposed converter was verified by experiments in a 6KW prototype designed for communication applications and operating at 100kHz.