• Journal of Power Electronics
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• v.15 no.1
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• pp.256-267
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• 2015

Grid-connected transformerless photovoltaic (PV) inverters (TPVIs) are increasingly dominating the market due to their higher efficiency, lower cost, lighter weight, and reduced size when compared to their transformer based counterparts. However, due to the lack of galvanic isolation in the low voltage grid interconnections of these inverters, the PV systems become vulnerable to leakage currents flowing through the grounded star point of the distribution transformer, the earth, and the distributed parasitic capacitance of the PV modules. These leakage currents are prohibitive, since they constitute an issue for safety, reliability, protection coordination, electromagnetic compatibility, and module lifetime. This paper investigates a wide range of multi-kW range power rating TPVI topologies and classifies them in terms of their leakage current attributes. This systematic classification places most topologies under a small number of classes with basic leakage current attributes. Thus, understanding and evaluating these topologies becomes an easy task. In addition, based on these observations, new topologies with reduced leakage current characteristics are proposed in this paper. Furthermore, the important efficiency and cost determining characteristics of converters are studied to allow design engineers to include cost and efficiency as deciding factors in selecting a converter topology for PV applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05a
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• pp.197-201
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• 2002

This paper presents optimized design, fabrication and thermal characteristics of micro-heaters for thermal MEMS (micro electro mechanical system) applications using SOI and trench structures. The micro-heaters are based on a thermal measurement principle and contains thermal isolation regions of 10 ${\mu}m$-thick Si membranes consisting of oxide-filled trenches in the SOI membrane rim. The micro-heaters were fabricated with Pt-RTD on the same substrate via MgO buff layer between Pt thin-film and $SiO_2$ layer. The thermal characteristics of micro-heater with trench-free SOI membrane structure was $280^{\circ}C$ at input power 0.9 W; in the presence of 10 trenches, it was $580^{\circ}C$ due to reduction of the external thermal loss. Therefore, a micro-heater with trenches in SOI membrane rim structure provides a powerful and versatile alternative technology for enhancing the performance of micro-thermal sensors and actuators.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.90-93
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STI CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. To resolve these problems, the development of slurry for CMP with high removal rate and high selectivity between each thin films was studied then it can be prevent the reasons of many defects by reasons of many defects by simplification of process that directly apply CMP process to STI structure without the reverse moat pattern process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.239-242
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• 2004

We investigated the nanotopography impact on the post-chemical mechanical polishing (post-CMP) oxide thickness deviation(OTD) of ceria slurry with a surfactant. Not only the surfactant but also the slurry abrasive size influenced the nanotopography impact. The magnitude of the post-CMP OTD increased with adding the surfactant in the case of smaller abrasives, but it did not increase in the case of larger abrasives, while the magnitudes of the nanotopography heights are all similar. We created a one-dimensional numercal simulation of the nanotopography impact by taking account of the non-Prestonian behavior of the slurry, and good agreement with experiment results was obtained.

• Journal of Surface Science and Engineering
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• v.31 no.5
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• pp.237-244
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• 1998

In this stydy, submicron shallow trenches applied to STI(shallow tench isolation) were etched using inductively coupled $CI_2$/HBr and $CI_2/N_2$plasmas and the physical and electrical defects remaining on the etched silicon trench surfaces and the effects of various annealing and oxidation on the removal of the defects were studied. Using high resolution electron microscopy(HRTEM), Physical defects were investigated on the silicon trench surfaces etched in both 90%$CI_2$/ 10%$N_2$ and 50%$CI_2$/50%HBr. Among the areas in the tench such as trench bottom, bottom edge, and sidewall, the most dense defects were found near the trench bottom edge, and the least dense defects were found near the trench bottom edge, and least dense defects compared to that etched with ment as well as hydrogen permeation. Thermal oxidation of 200$\AA$ atthe temperature up to $1100^{\circ}C$apprars not to remove the defects formed on the etched silicon trenches for both of the etch conditions. To remove the physicall defects, an annealing treatment at the temperature high than $1000^{\circ}C$ in N for30minutes was required. Electrical defects measured using a capacitance-voltage technique showed the reduction of the defects with increasing annealing temperature, and the trends were similar to the results on the physical defects obtained using transmission electron microscopy.

• ETRI Journal
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• v.43 no.3
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• pp.414-426
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• 2021

In the task of data routing in Internet of Things enabled volatile underwater environments, providing better transmission and maximizing network communication performance are always challenging. Many network issues such as void holes and network isolation occur because of long routing distances between nodes. Void holes usually occur around the sink because nodes die early due to the high energy consumed to forward packets sent and received from other nodes. These void holes are a major challenge for I-UWSANs and cause high end-to-end delay, data packet loss, and energy consumption. They also affect the data delivery ratio. Hence, this paper presents an energy efficient watchman based flooding algorithm to address void holes. First, the proposed technique is formally verified by the Z-Eves toolbox to ensure its validity and correctness. Second, simulation is used to evaluate the energy consumption, packet loss, packet delivery ratio, and throughput of the network. The results are compared with well-known algorithms like energy-aware scalable reliable and void-hole mitigation routing and angle based flooding. The extensive results show that the proposed algorithm performs better than the benchmark techniques.

• International Journal of Aerospace System Engineering
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• v.9 no.1
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• pp.1-15
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• 2022

Pyrotechnic initiators provide a source of pyrotechnic energy used to initiate a variety of space mechanisms. Pyrotechnic systems build in electromagnetic environment that may lead to critical or catastrophic hazards. Special precautions are need to prevent a pulse large enough to trigger the initiator from appearing in the pyrotechnic firing circuits at any but the desired time. The EMC verification shall be shown by analysis or test that the pyrotechnic systems meets the requirements of inadvertent activation. The MIL-STD-1576 and two range safeties, AFSPC and CSG, require the safety margin for electromagnetic potential hazards to pyrotechnic systems to a level at least 20 dB below the maximum no-fire power of the EED. The PC23 is equivalent to NASA standard initiator and the 1EPWH100 squib is ESA standard initiator. This paper verifies the two safety margins for electromagnetic potential hazards. The first is verified by analyzing against a RF power. The second is verified by testing against a DC current. The EMC safety margin requirement against RF power has been demonstrated through the electric field coupling analysis in differential mode with 21 dB both PC23 and 1EPWH100, and in common mode with 58 dB for PC23 and 48 dB for 1EPWH100 against the maximum no-fire power of the EED. Also, the EMC safety margin requirement against DC current has been demonstrated through the electrical isolation test for the pyrotechnic firing circuits with greater than 20 dB below the maximum no-fire current of the EED.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.261-278
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• 2003

Concepts.Wafer-Level Chip-Scale Concept with Handling Substrate.Low Accuracy Placement Layout with Isolation Trench.Possible Pitch of Interconnections down to $10{\mu}{\textrm}{m}$ (Sn-Grains).Wafer-to-Wafer Equipment Adjustment Accuracy meets this Request of Alignment Accuracy (+/-1.5 ${\mu}{\textrm}{m}$).Adjustment Accuracy of High-Speed Chip-to-Wafer Placement Equipment starts to meet this request.Face-to-Face Modular / SLID with Flipped Device Orientation.interchip Via / SLID with Non-Flipped Orientation SLID Technology Features.Demonstration with Copper / Tin-Alloy (SLID) and W-InterChip Vias (ICV).Combination of reliable processes for advanced concept - Filling of vias with W as standard wafer process sequence.No plug filling on stack level necessary.Simultanious formation of electrical and mechanical connection.No need for underfiller: large area contacts replace underfiller.Cu / Sn SLID layers $\leq$ $10{\mu}{\textrm}{m}$ in total are possible Electrical Results.Measurements of Three Layer Stacks on Daisy Chains with 240 Elements.2.5 Ohms per Chain Element.Contribution of Soldering Metal only in the Range of Milliohms.Soldering Contact Resistance ($0.43\Omega$) dominated by Contact Resistance of Barrier and Seed Layer.Tungsten Pin Contribution in the Range of 1 Ohm

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.69-78
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• 1999

In this paper, direct conversion receiver was designed to even harmonic anti-paralled diode pair ring mixer. Using a second harmonic component of LO instead of LO signal and RF signal are mixed by SHP(Sub Harmonic Pumped) mixer with anti-parallel diode pair. Canceling the harmonics of LO signal in ring mixer, SHP mixer using anti-parallel diode pair could mostly reduce the radiation of LO signal through a input port the most, good isolation characteristic, and low spurious characteristic by LO signal was shown over broad band. The produced SHP mixer showed LO/IF, RF/IF and LO/RF isolation was 24.6dB,36.2dB and 22.5dB respectively. And conversion loss was measured 15.6dB, IF output -35.6dBm with -20dBm RF input and 5.5dBm LO signal. 1dB compression point of If signal, in respect to RF signal, was found at the 0dbm RF signal.

• Journal of the Korean Vacuum Society
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• v.6 no.4
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• pp.343-347
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• 1997

The dependence of compensation mechanism in $P^+$-InGaAs layer implanted with oxygen on the annealing temperatures was investigated. The oxygen implantation was performed for electrical isolation. The conductivity was controlled by damage related traps below $500^{\circ}C$. For the temperature of 500 to $600^{\circ}C$, oxygen began to show the chemical effect of compensating the acceptors due to activation and type conversion (plongrightarrown-type) occurred at $600^{\circ}C$. This indicates that the defects generated by the chemical activity of oxygen increased with increasing annealing temperature, where activation energy of 24.2 meV was obtained. It is attributed to the formation of native defects, such as In interstitials, acting as shallow donor in InGaAs. Above $600^{\circ}C$, the interstitial Be atoms become reactivated and the n-type conductivity decreases.