• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.65-70
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• 2013

A 0.18-${\mu}m$ 3.3 V grounded-gate NMOS (GGNMOS) I/O cell array for timing controller (TCON) application is proposed for improving electrical overstress (EOS) robustness. The improved cell array consists of 20 GGNMOS, 4 inserted well taps, 2 end-well taps and shallow trench isolation (STI). Technology computer-aided design (TCAD) simulation results show that the inserted well taps and extended drain contact gate spacing (DCGS) is effective in preventing EOS failure, e.g. local burnout. Thermodynamic models for device simulation enable us to obtain lattice temperature distributions inside the cells. The peak value of the maximum lattice temperature in the improved GGNMOS cell array is lower than that in a conventional GGNMOS cell array. The inserted well taps also improve the uniformity of turn-on of GGNMOS cells. EOS test results show the validity of the simulation results on improvement of EOS robustness of the new GGNMOS I/O cell array.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.3
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• pp.132-138
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• 2005

In this paper a DPDT(Double-Pole Double Through) switch with defected ground structure(DGS) is proposed. The equivalent circuit for the proposed switch structure is derived according to based on equivalent circuit of proposed DGS unit structure. The equivalent circuit parameters of DGS unit are extracted by using the circuit analysis method. The on/off operation of the proposed switch is obtained by varying the capacitance of the varactor diode at the defected ground plane. In the case of ON state, the insertion loss of the fabricated DPDT was shown under 1dB. And in OFF state, we found the rejection characteristic over 20dB at the designed frequency 2.45GHz. The experimental results show excellent insertion loss at on state and isolation at off state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.211-213
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• 1999

In this paper, we documented the controlling oxide removal amount on the pattern wafer using removal rate and removal thickness of blanket wafer. There was the strong correlation relationship for both(correlation factor:0.7109). So, we could confirm the repeatability as applying for STI CMP process from the obtained linear formular. As the result of repeatability test, the difference of calculated polishing time and actual polishing time was 3.48 seconds based on total 50 lots. If this time is converted into the thickness, it is from 104$\AA$ to 167$\AA$. It is possible to be ignored because it is under the process margin.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.11
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• pp.663-669
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• 1999

This paper presents new self excited DC-DC converters such as Buck-boost type, Buck type and also non-inverting Buck-boost type. The proposed converters has the following advantages: simple topology, small number of circuit components, easy control method. Therefore, these converters are suitable for the portable appliances with battery source. It is especially suited for low power DC-DC conversion applications where non isolation output power is usually required. The steady state characteristics of proposed self exciting Buck-boost DC-DC converter are analysis and the result shows good agreement with experimental value. Furthermore the experimental results for 50W class self oscillating Buck-boost DC-DC converter have been obtained, which demonstrate the high efficiency and good performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.411-414
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• 1998

In this paper, the silicon-nitride membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PT layer as a IR detection layer was deposited on the membrane and its characteristics were measured. The attack of PT layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer can be solved through the method of bonding/etching of silicon wafer. Because the PT layer of c-axial orientation rained thermal polarization without polling, the more integration capability can be achieved. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by IR detector, and the bonding interface was observed by SEM. The polarization characteristics and the dielectric characteristics of the PT layer were measured, too.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.9
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• pp.771-774
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.815-819
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• 1998

The silicon-nirtide membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PRO($PbTiO_3$ ) layer for a IR detection was coated on the membrane and its characteristics were measured. The a attack of PTO layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer were eliminated through the method of bonding/etching of silicon wafer. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by the PTO layer were measured, too.

• Advances in robotics research
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• v.2 no.1
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• pp.99-112
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• 2018

The main contribution of this work is the design of a field programmable gate array (FPGA) based ARX-Laguerre proportional-integral observation (PIO) system for fault detection and identification (FDI) in a multi-input, multi-output (MIMO) nonlinear uncertain dynamical robot manipulators. An ARX-Laguerre method was used in this study to dynamic modeling the robot manipulator in the presence of uncertainty and disturbance. To address the challenges of robustness, fault detection, isolation, and estimation the proposed FPGA-based PI observer was applied to the ARX-Laguerre robot model. The effectiveness and accuracy of FPGA based ARX-Laguerre PIO was tested by first three degrees of the freedom PUMA robot manipulator, yielding 6.3%, 10.73%, and 4.23%, average performance improvement for three types of faults (e.g., actuator fault, sensor faults, and composite fault), respectively.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.9
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• pp.422-430
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• 2005

This paper describes experimental analysis of UPFC, which is composed of cascaded H-bridge modules and single-phase multi-winding transformers for isolation. The operational characteristic was analyzed through experimental works with a scaled model, and simulation results with PSCAD/EMTDC. The UPFC proposed in this paper can be directly connected to the transmission line without series injection transformers. It has flexibility to expand the operation voltage by increasing the number of H-bridge modules. The analysis results can be utilized to design the actual WFC system applicable for the transmission system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.350-353
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• 1999

This Paper Presents the optimized design of micro-heaters using 501(Si-on-insulator) substrate and oxide-filled trench structure In order to justify a lumped model approximation and thermal boundary assumptions, two-dimensional FDM(finite difference among which conduction is the dominant heat dissipation path. Compared with no-trenchs on the SOI structure, the micro-heaters with trench structures has properties of low heater loss and good thermal isolation. The simulation results show that the heater loss decreases as the number. width and distance of trenchs increases.