• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.40 no.12
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• pp.1040-1047
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• 2012

This paper presents a fault diagnosis algorithm of control surfaces of small fixed-wing aircraft to reduce maintenance cost or to improve repair efficiency by estimation of fault occurrence or part replacement periods. The proposed fault diagnosis algorithm consists of ANPSD (Averaged Normalized Power Spectral Density), PCA (Principle Component Analysis), and GC (Geometric Classifier). ANPSD is used for frequency-domain vibration testing. PCA has advantage to extract compressed information from ANPSD. GC has good properties to minimize errors of the fault detection and isolation. The algorithm was verified by the accelerometer measurements of the scaled normal and faulty ailerons and the test results show that the algorithm is suitable for the detection and isolation of the control surface faults. This paper also proposes solutions for some kind of implementation problems.

• Proceedings of the KOSOMBE Conference
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• v.1996 no.11
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• pp.277-280
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• 1996

We have developed a ground-isolation circuit in order to reduce the noise of the internal controller system for the total artificial heart(TAH) and ventricular assist device(VAD). Using the ground-isolation technique, we could transmit the analog target signal to other pheriperal device including IBM PC via RS232C and polygraph, with no noise. Experimental results of VAD showed that there was less impulsive noise in current signal which caused in our previous conventional system. Therefore it could be proved that implementation of isolation technique is very effective to improve the signal to noise ratios of analog signal transmission for TAH or VAD.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2504-2508
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• 1998

In this paper, we propose the new detecting method for three dimensional piezoresistive silicon accelerometer. Furthermore the accelerometer is formed to have endurance for high temperature by perfect isolation of the piezoresistors using Silicon On Insulator(SOI) wafer. Sensor size are optimized with analytical formulae and extended with FEM simulation for the more detailed results. The accelerometer was fabricated by bulk micromachining techonology. We measured the temperature characteristics and the output characteristics, and the both characteristics were compared with the simulated results

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.535-538
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• 1994

In this paper, an isolated ZVS-PWM boost converter is proposed for single stage line conversion. For power factor correction, we used the half bridge topology at the primary side of isolation transformer permitting switching devices to operate under ZVS by using circuit parastics and operating at a fixed duty ratio near 50%. Thus the relatively continuous input current distortion and small size input filter are also achievable. The ZVS-PWM boost operation of the proposed converter can be achieved by using the boost inductor $L_f$, main switch $Q_3$, and simple auxiliary circuit at the secondary side of isolation transformer. The secondary side circuit differ from a conventional PWM boost converter by introduction a simple auxiliary circuit. The auxiliary circuit is actived only during a short switching transition time to create the ZVS condition for the main switch as that of the ZVT-PWM boost converter. With a single stage, it is possible to achieve a sinusoidal line current at unity power factor as well as the isolated 48V DC output. Comparing to the two stage schemes, overall effiency of the proposed converter is highly improved due to the effective ZVS of all devices as well as single stage power conversion. Thus, it can be operated at high switching frequency allowing use of small size input filter. Minimum voltage and current stress make it high power application possible.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.291-293
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• 2000

In 64M DRAM, sub-1/4m NMOSFETs with STI(Shallow Trench Isolation), anomalous hump phenomenon of subthreshold region, due to capped p-TEOS/SiN interlayer induced defect, is reported. The hump effect was significantly observed as channel length is reduced, which is completely different from previous reports. Channel Boron dopant redistribution due to the defect should be considered to improve hump characteristics besides consideration of STI comer shape and recess.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1292-1295
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• 2000

In this paper, we proposed a new single-stage single-switch power factor correction(S-4 PFC) converter with output electrical isolation. The configuration of this converter is achieved by combining a fly back circuit and a forward circuit in one power stage. To verify the theoretical analysis of the proposed converter, a design example is given with its Pspice simu-lation and experimental results.

• Transactions on Electrical and Electronic Materials
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• v.3 no.3
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• pp.18-20
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• 2002

In sub-l/4 ${\mu}{\textrm}{m}$ NMOSFET with STI (Shallow Trench Isolation), the anomalous hump phenomenon of subthreshold region, due to capped p-TEOS/SiN induced defect, is reported. The hump effect was significantly observed as channel length is reduced, which is completely different from previous reports. Channel boron dopant redistribution due to the defect should be considered to improve hump characteristics besides considerations of STI comer and recess. 130

• Journal of Power Electronics
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• v.8 no.2
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• pp.109-120
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• 2008

In this paper, a novel delta/double-fork transformer based 18-pulse full-wave AC-DC converter is designed, modeled, simulated and developed to feed isolated DC varying loads. The proposed AC-DC converter is used for low voltage and large current DC loads in applications such as electrowinning, where isolation is required mainly for stepping down the supply voltage. The proposed converter improves power quality at AC mains and meets IEEE-519 standard requirements at varying loads.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1352-1364
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• 2013

This paper describes a novel structure for single phase Unified Power Quality Conditioner-Distributed Generation (UPQC-DG) with direct grid connected DC-AC converter for low DC output DG systems which can be used not only for compensation of power quality problems but also for supplying of load power partly. This converter has been composed of one full-bridge inverter, one three winding high frequency transformer with galvanic isolation and two cycloconverters. Proper control based on Input Output feedback Linearization is used to tracking the reference signals. The simulation and experimental results are presented to confirm the validity of the proposed approach.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.339-341
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• 1997

From this first studies, We have investigated the latch-up characteristics of various CMOS well structures possible with high energy ion implantation processes. In this study, we also investigated those of STI(Shallow Trench Isolation} structures with varing n+/p+ spacing and the depth of trench. STI structure is formed by T-SUPREM4 process simulator, and then latch-up simulations for each case were performed by MEDICI device simulator for latch-up immunity improvement. STI is very effective to preventing the degradation of latch-up characteristics as the n+/p+ spacing is reduced. These studies will allow us to evaluate each technology and suggest guidelines for the optimization of latch-up susceptibility.