• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.2
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• pp.1-6
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• 2021

In this paper, an efficient implementation of AES encryption algorithm is presented for CCTV image security using C# language. In this approach, an efficient S-Box is first designed for reducing the computation time which is required in each round process of AES algorithm, and then an CCTV image security system is implemented on the basis of this algorithm on a composite field GF(((22)2)2). In addition, the shared S-Box structure is designed for realizing the minimized memory space, which is used in each round transformation and key scheduling processes. Through performance evaluation, it was confirmed that the proposed method is more efficient than the existing method. The proposed CCTV system in C# language using Visual studio 2010.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.3
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• pp.545-550
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• 2018

Ultra-lightweight block cipher CHAM, consisting of simple addition, rotation, and eXclusive-or operations, enables the efficient implementations over both low-end and high-end Internet of Things (IoT) platforms. In particular, the CHAM block cipher targets the enhanced computational performance for the low-end IoT platforms. In this paper, we introduce the efficient implementation techniques to minimize the memory consumption and optimize the execution timing over 8-bit AVR IoT platforms. To achieve the higher performance, we exploit the partly iterated expression and arrange the memory alignment. Furthermore, we exploit the optimal number of register and data update. Finally, we achieve the high RANK parameters including 29.9, 18.0, and 13.4 for CHAM 64/128, 128/128, and 128/256, respectively. These are the best implementation results in existing block ciphers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.1-8
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• 2018

Recently, the convolutional neural network shows high performance in many computer vision tasks. However, convolutional neural networks require enormous amount of operation, so it is difficult to adopt them in the embedded environments. To solve this problem, many studies are performed on the ASIC or FPGA implementation, where an efficient representation method is required. The fixed-point representation is adequate for the ASIC or FPGA implementation but causes a performance degradation. This paper proposes a separate optimization of representations for the convolutional layers and the batch normalization layers. With the proposed method, the required bit width for the convolutional layers is reduced from 16 bits to 10 bits for the ResNet-50 neural network. Since the computation amount of the convolutional layers occupies the most of the entire computation, the bit width reduction in the convolutional layers enables the efficient implementation of the convolutional neural networks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.7
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• pp.1608-1616
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• 2015

This paper describes an efficient hardware implementation of lightweight encryption algorithm LEA-128/192/256 which supports for three master key lengths of 128/192/256-bit. To achieve area-efficient and low-power implementation of LEA crypto- processor, the key scheduler block is optimized to share hardware resources for encryption/decryption key scheduling of three master key lengths. In addition, a parallel register structure and novel operating scheme for key scheduler is devised to reduce clock cycles required for key scheduling, which results in an increase of encryption/decryption speed by 20~30%. The designed LEA crypto-processor has been verified by FPGA implementation. The estimated performances according to master key lengths of 128/192/256-bit are 181/162/109 Mbps, respectively, at 113 MHz clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.6
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• pp.15-24
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• 2006

Recently, the importance of the area efficient implementation of cryptographic algorithm for the portable device is increasing. Previous ARIA(Academy, Research Institute, Agency) implementation styles that usually concentrate upon speed, we not suitable for mobile devices in area and power aspects. Thus in this paper, we present an area efficient AR processor which use 32-bit architecture. Using new implementation technique of diffusion layer, the proposed processor has 11301 gates chip area. For 128-bit master key, the ARIA processor needs 87 clock cycles to generate initial round keys, n8 clock cycles to encrypt, and 256 clock cycles to decrypt a 128-bit block of data. Also the processor supports 192-bit and 256-bit master keys. These performances are 7% in area and 13% in speed improved results from previous cases.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.20 no.1
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• pp.3-16
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• 2010

Recently in the field of the wireless sensor network, many researchers are attracted to pairing cryptography since it has ability to distribute keys without additive communication. In this paper, we propose efficient hardware implementation of ${\eta}_T$ pairing which is one of various pairing scheme. we suggest efficient hardware architecture of ${\eta}_T$ pairing based on parallel processing and register/resource optimization, and then we present the result of our FPGA implementation over GF($2^{239}$). Our implementation gives 15% better result than others in Area Time Product.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1999.04a
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• pp.423-423
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• 1999

• ETRI Journal
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• v.43 no.3
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• pp.571-571
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• 2021

• The Pure and Applied Mathematics
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• v.5 no.2
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• pp.133-142
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• 1998

A simple mathematical theory is developed on the periodicity of elementary polar functions. The periodicity plays an important role in efficient plotting of some closed polar curves, without the excessive use of plotting devices and materials. An efficient plotting algorithm utilizing the periodicity is proposed and its implementation by a Mathematica program is introduced for a family of closed polar functions.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1053-1056
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• 1999

Video On Demand servers generally require massive disk storages for storing many video data. Many researches have been done on the topics of efficient allocation of movies in disks. This paper, We describe efficient disk placement techniques and implement storage system with SCSI and PCI Bus interface for efficient data handling. This paper also proposes a logical zone reconstruction method for the SCAN data placement technique. The proposed method reconstructs physical zones into logical zones by split and merge operations.