• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.76.1-76.1
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• 2010

Furnace를 이용한 $POCl_3$ 확산 공정은 실리콘 태양전지 제작과정에서 일반적으로 이용되는 에미터 층 형성 공정이다. 하지만, 확산 공정을 통해 P-N Junction을 형성할 경우 전면과 후면의 contact현상이 발생하게 되고 이를 제거하기 위해 Edge isolation 공정을 거치게 된다. 최근에는 레이저로 V 모양의 홈을 형성하는 방법이 이용되고 있다. 본 연구에서는 p-type 실리콘 웨이퍼 기판에 insulating barrier를 형성하여 edge isolation 공정을 없앤 Non-edge isolation공정을 제시한다. Non p-type 실리콘 웨이퍼에 insulating barrier를 형성한다. Insulating barrier가 형성된 BOE용액과 KOH에서의 견딤성 실험을 진행 하였다. 이후, p-type 단결정 실리콘 태양전지의 확산 공정을 진행하여 Non edge isolation 공정을 진행한 경우와 laser를 이용한 edge isolation 공정을 진행한 태양전지를 제작하여 특성을 비교하였다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.5
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• pp.851-856
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• 2017

Research on the edge isolation process of typical polycrystalline silicon solar cells was carried out using laser scribing equipment. The voltage-current characteristics of the solar cell before and after laser scribing were analyzed using a solar simulator. Current density and efficiency increased as the fill factor of the solar cell remained constant after the laser scribing process. The efficiency of the solar cell can be increased in a short time by the edge isolation process performed via a laser scribing process. The polycrystalline silicon solar cell was made into a series electrode, and the efficiency of the solar cell increased because the width of the solar cell was narrowed and the active region was widened by the laser scribing process.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.344-345
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• 2012

The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

• Journal of the Korea Society for Simulation
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• v.11 no.1
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• pp.23-30
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• 2002

An STI(Shallow Trench Isolation) by using a CMP(Chemical Mechanical Polishing) process has been one of the key issues in the device isolation[1] In this paper we fabricated N, P-MOSFEET tall analyse hump characteristics in various rounding oxdation thickness(ex : Skip, 500, 800, 1000$\AA$). As a result we found that hump occurred at STI channel edge region by field oxide recess. and boron segregation(early turn on due to boron segregatiorn at channel edge). Therefore we improved that hump occurrence by increased oxidation thickness, and control field oxide recess( 20nm), wet oxidation etch time(19HF,30sec), STI nitride wet cleaning time(99HF, 60sec+P 90min) and fate pre-oxidation cleaning time (U10min+19HF, 60sec) to prevent hump occurring at STI channel edge.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.7
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• pp.311-315
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• 2002

Chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD), inter-level dielectric (ILD) layers of multi-layer interconnections. In this paper, we studied the characteristics of polishing pad, which can apply shallow trench isolation (STI)-CMP process for global planarization of multi-level interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was detected less than 2 on JR111 pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and device yield.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.319-319
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• 2012

현재 폭넓게 이용되고 있는 STI (Shallow Trench Isolation) 공정에서 active edge 부분에 발생하는 기생 transistor의 subthreshold hump 특성을 제어하는 연구가 활발히 이루어지고 있다. 일반적으로 STI 공정을 이용하는 MOSFET에서 active edge 부분의 얇게 형성된 gate oxide, sharp한 active edge 형성, STI gap-fill 공정 중에 생기는 channel dopant out-diffusion은 subthreshold hump 특성의 주된 요인이다. 이와 같은 문제점을 해결하기 위해 active edge rounding process와 channel dopant compensation의 implantation을 이용하여 subthresold hump 특성 개선을 연구하였다. 본 연구는 STI 공정에 필요한 wafer와 phosphorus를 함유한 wafer를 한 chamber 안에서 auto-doping하는 방법을 이용하여 subthresold hump 특성을 구현하였다. phosphorus를 함유한 wafer에서 빠져나온 phosphorus가 STI 공정중인 wafer로 침투하여, active edge 부분의 channel dopant인 boron 농도를 상대적으로 낮춰 active edge 부분의 가 감소하고 leakage current를 증가시킨다. transistor의 channel length, gate width이고, wafer#No가 클수록 phosphorous를 함유한 wafer까지의 거리는 가까워진다. wafer #01은 hump 특성이 없고, wafer#20은 에서 심한 subthreshold hump 특성을 보였다. channel length 고정, gate width를 ~으로 가변하여 width에 따른 영향을 실험하였다. active 부분에 대한 SCM image로 확인된 phosphorus에 의한 active edge 부분의 boron 농도 감소와 gate width vs curve에서 확인된 phosphorus에 의한 감소가 narrow width로 갈수록 커짐을 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.127-132
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• 2012

In this paper, the edge effects of proposed structure in active region for high voltage in shallow trench isolation for very large integrated MOSFET were simulated. Shallow trench isolation (STI) is a key process component in CMOS technologies because it provides electrical isolation between transistors and transistors. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.421-424
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• 2004

As the deep sub-micron devices are recently integrated high package density, novel process method for sub $0.1{\mu}m$ devices is required to get the superior thin gate oxide characteristics and reliability. However, few have reported on the electrical quality and reliability on the thin gate oxide. In this paper I will recommand a novel shallow trench isolation structure for thin gate oxide $30{\AA}$ of deep sub-micron devices. Different from using normal LOCOS technology, novel shallow trench isolation have a unique 'inverse narrow channel effects' when the channel width of the devices is scaled down shallow trench isolation has less encroachment into the active device area. Based on the research, I could confirm the successful fabrication of shallow trench isolation(STI) structure by the SEM, in addition to thermally stable silicide process was achiever. I also obtained the decrease threshold voltage value of the channel edge and the contact resistance of $13.2[\Omega/cont.]$ at $0.3{\times}0.3{\mu}m^2$. The reliability was measured from dielectric breakdown time, shallow trench isolation structure had tile stable value of $25[%]{\sim}90[%]$ more than 55[sec].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.5
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• pp.1009-1019
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• 2017

Mobile Edge Computing(MEC) is a emerging technology to cope with mobile traffic explosion and to provide a variety of services having specific requirements by means of running some functions at mobile edge nodes directly. For instance, caching function can be executed in order to offload mobile traffics, and safety services using real time video analytics can be delivered to users. So far, a myriad of methods and architectures for personalized service recommendation have been proposed, but there is no study on the subject which takes unique characteristics of mobile edge computing into account. To provide personalized services, acquiring users' context is of great significance. If the conventional personalized service model, which is server-side oriented, is applied to the mobile edge computing scheme, it may cause context isolation and privacy issues more severely. There are some advantages at mobile edge node with respect to context acquisition. Another notable characteristic at MEC scheme is that interaction between users and applications is very dynamic due to temporal relation. This paper proposes the local service recommendation platform architecture which encompasses these characteristics, and also discusses the personalized service recommendation mechanism to be able to mitigate context isolation problem and privacy issues.

• Journal of Environmental Impact Assessment
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• v.17 no.5
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• pp.279-288
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• 2008

Vertical forest distribution is one of the important factors to understand various ecological mechanism such as succession, disturbance and environmental effects. LiDAR data provide information, both the horizontal and vertical distribution of forest structure. The laser scanner survey provided a point cloud, in which the x, y, and z coordinates of the points are known. The objectives of this study were 1) to analyze factors of forest structure such as individual tree isolation, tree height, canopy closure and tree density using LiDAR data and 2) to compare the forest structure between outer and interior forest. The paper conducted to extract the individual tree using watershed algorithm and to interpolate using the first return of LiDAR data for yielding digital surface model (DSM). The results of the study show characters of edge such as more isolated individual trees, higher density, lower canopy closure, and lower tree height than those of interior forest. LiDAR data is to be useful for analyzing of forest structure. Further study should be undertaken with species for more accurate results.