• Journal of IKEEE
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• v.26 no.1
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• pp.119-123
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• 2022

This paper propose a new ESD protection device suitable for 12V class applications by adding a self-biasing structure to an ESD protection device with high holding voltage due to additional parasitic bipolar BJT. To verify the operating principle and electrical characteristics of the proposed device, current density simulation and HBM simulation were performed using Synopsys' TCAD Simulation, and the operation of the additional self-biasing structure was confirmed. As a result of the simulation, it was confirmed that the proposed ESD protection device has a higher level of holding voltage compared to the existing ESD protection device. It is expected to have high area efficiency due to the dual structure and sufficient latch-up immunity in 12V-class applications.

• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• Journal of IKEEE
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• v.13 no.1
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• pp.19-29
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• 2009

For two input ESD protection schemes utilizing the NMOS protection device or the lvtr_thyristor protection device, which is suitable for high-frequency CMOS ICs, we attempt an in-depth comparison study on the HBM ESD protection level in terms of lattice heating inside the protection devices and the peak voltage applied to the gate oxides in the input buffer through DC, mixed-mode transient, and AC analyses utilizing the 2-dimensional device simulator. For this purpose, we suggest a method for the equivalent circuit modeling of the input HBM test environment for the CMOS chip equipped with the input ESD protection circuit. And by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can be occurred in a real HBM test. In this procedure, we explain about the strength and weakness of the two protection schemes as an input protection circuit for high-frequency ICs, and suggest guidelines relating to the design of the protection devices.

• Journal of IKEEE
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• v.25 no.1
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• pp.168-173
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• 2021

In this paper, we propose a new structure of ESD protection device that achieves improved electrical characteristics through structural change of LVTSCR, which is a general ESD protection device. In addition, it applies N-Stack technology for optimized design in the ESD Design Window according to the required voltage application. The N-Well area additionally inserted in the existing LVTSCR structure provides an additional ESD discharge path by electrically connecting to the anode, which improves on-resistance and temperature characteristics. In addition, the short trigger path has a lower trigger voltage than the existing LVTSCR, so it has excellent snapback characteristics. In addition, Synopsys' T-CAD Simulator was used to verify the electrical characteristics of the proposed ESD protection device.

• Journal of IKEEE
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• v.19 no.2
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• pp.265-270
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• 2015

In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.88-97
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• 1993

Electrostatic Discharge(ESD) is one of the major reliability, issues for today's VLSI production. Since the gate oxide with a thickness of 100~300$\AA$ is vulnerable to several thousand volt of ESD surge, it is necessary to control the ESD events and design an efficient protection circuit. In this paper, physical mechanism of the catastrophic ESD damage is investigated by transient analysis based upon Human Body Model(HBM). Using two-dimensional electrothermal simulator, we study the failure mechanism of the output protection devices by ESD and discuss the design issues for the optimun protection network.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.12
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• pp.589-595
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• 2004

The ESD protection characteristic of chip varistors on a circuit board can not be analyzed by using a conventional circuit simulator due to its microwave characteristic. Thus, by employing Agilent's microwave circuit simulator ADS, we showed that the ESD Protection characteristic or chip varistors can be investigated. order to got more precise simulation results, a chip varistor model was extracted from the electrical characteristic of a TDK's chip varistor and the distributed circuit based pattern was designed as the ESD propagation path. The simulation results showed that the ESD protection characteristic of a chip varistors can be improved drastically by reducing the ESD propagation path.

• Journal of IKEEE
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• v.21 no.2
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• pp.150-153
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• 2017

In this paper, a structure of GCNMOS based ESD protection circuit using floating-body technique is proposed. TCAD simulation of Synopsys was used to compare with the conventional GGNMOS and GCNMOS. Compared with the conventional GCNMOS, the proposed ESD protection circuit has lower trigger voltage and faster turn-on-time than conventional circuit because of the added NMOSFET. In the simulation result, the triggering voltage of the proposed ESD protection circuit is 4.86V and the turn-on-time is 1.47ns.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.875-878
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• 2002

전자 상거래의 발전과 더불어 디지털화된 모든 컨텐츠는 인터넷을 통해 배포되어 이용되고 있다. 소프트웨어도 예외는 아니어서 기존에 오프라인을 통해 유통되던 소프트웨어들이 ESD(Electronic software Distribution)를 통해 온라인으로 유통되고 있다. 그러나 기존의 ESD 모델들은 소프트웨어의 불법복제문제를 해결하지 못하고 저작권보호에 미흡하다는 단점이 있다. 이에 본 논문에서는 ESD에 DRM기술을 사용하여 소프트웨어의 불법사용방지와 다양한 사용권한 제어가 가능한 P-ESD(Protection-ESD) 메커니즘을 제안한다. 제안한 모델은 불법사용을 방지하여 소프트웨어 저작권을 보호하고 다양한 지불방법을 제공한다.