• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.11
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• pp.97-106
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• 1992

In integrated circuits, protection circuits are required to protect the internal nodes from the harmful ESD(Electrostatic discharge). This paper discusses the characteristics of the circuit components in ESD protection circuitry in order to analyze the ESD phenomina, and the design methodalogy of ESD protection circuits, using test pattern with a variation of the number of diode and transistor. The test devices are fabricated using a 0.8$\mu$m CMOS process. SPICE simulation was also carried out to relate output node voltage and measured ESD voltage. With increasing number of diodes and transistors in protection circuit, the ESD voltage also increases. The ESD voltage of the bi-directional circuit for both input and output was 100-300[V], which in higher than that of only output(uni-directional) circuit. In addition, the ESD protection circuit with the diode under the pad region was useful for the reduction of chip size and parasitic resistance. In this case, ESD voltage was improved to a value about 400[V].

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.11
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• Journal of IKEEE
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• v.21 no.3
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• pp.234-239
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• 2017

In this paper, we propose an ESD (Electrostatic Discharge) protection circuit based on a new structure of SCR (Silicon Controlled Rectifier) embedded with PMOS structure. The proposed ESD protection circuit has a built-in PMOS structure and has a latch-up immunity characteristic and an improved tolerance characteristic. To verify the characteristics of the proposed ESD protection circuit and to analyze its operating characteristics, we compared and analyzed the characteristics of the existing ESD protection circuit using TCAD simulation. Simulation results show that the proposed protection ESD protection circuit has superior latch-up immunity characteristics like the existing SCR-based ESD protection device HHVSCR (High Holding Voltage SCR). Also, according to the results of the HBM (Human Body Model) maximum temperature test, the proposed ESD protection circuit has a maximum temperature value of 355K, which is about 20K lower than the existing HHVSCR 373K. In addition, the proposed ESD protection circuit with improved electrical characteristics is designed by applying N-STACK technology. As a result of the simulation, the proposed ESD protection circuit has a holding voltage characteristic of 2.5V in a single structure, and the holding voltage increased to 2-STACK 4.2V, 3-STACK 6.3V, 4-STACK 9.1V.

• Journal of IKEEE
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• v.28 no.2
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• pp.204-208
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• 2024

In this paper, we propose an ESD protection circuit that applies structural changes to LVTSCR, a general low-voltage ESD protection circuit, to improve the current driving capability (IEC-ESD) characteristics of the ESD protection circuit. Power consumption was minimized by separating the area where the electric field and ESD current path are formed in the LVTSCR structure, and the electrical characteristics were analyzed and current driving characteristics were improved. Structural problems resulting from deterioration of system level characteristics were analyzed through simulation, and the characteristics were verified by reflecting this. The electrical characteristics of the proposed ESD protection circuit were verified using a TCAD simulator and analyzed through HBM modeling and system level modeling. In addition, silicon production and HBM 10kV characteristics were verified through DB-Hitek 0.18um BCD process.

• ETRI Journal
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• v.38 no.2
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• pp.272-279
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• 2016

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.64-70
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• 1994

In this paper, we inverstigated how a parricular internal inverter circuit, which is located far from the input protection in CMOS DRAM, can be easily damaged by external ESD stress, while the protection circuit remains intact. It is shown in a mega bit DRAM that the internal circuit can be safe from ESD by simply improving the input protection circuit. An inverter, which consists of a relatively small NMOSFET and a very large PMOSFET, is used to speed up DRAMs, and the small NMOSFET is vulnerable to ESD in case that the discharge current beyond the protection flows through the inverter to Vss or Vcc power lines on chip. This internal circuit damage can not be detected by only measuring input leakage currents, but by comparing the standby and on operating current before and after ESD stressing. It was esperimentally proven that the placement of parasitic bipolar transistor between input pad and power supply is very effective for ESD immunity.

• Journal of IKEEE
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• v.27 no.3
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• pp.258-264
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• 2023

This paper proposes an LDO regulator with a built-in ESD (Electro Static Discharge) protection circuit to effectively operate and prevent destruction of the LDO (Low Drop Out) regulator according to the load current. The proposed LDO regulator can more effectively adjust the gate node voltage of the pass transistor according to the output voltage of the LDO regulator by using an additional feedback current circuit structure. In addition, it is expected to have high reliability for the ESD situation by embedding a new structure that increases the holding voltage by about 2V by reducing the current gain on the SCR loop by adding a P+ bridge to the existing ESD protection device.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.12
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• pp.589-595
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• 2004

The ESD protection characteristic of chip varistors on a circuit board can not be analyzed by using a conventional circuit simulator due to its microwave characteristic. Thus, by employing Agilent's microwave circuit simulator ADS, we showed that the ESD Protection characteristic or chip varistors can be investigated. order to got more precise simulation results, a chip varistor model was extracted from the electrical characteristic of a TDK's chip varistor and the distributed circuit based pattern was designed as the ESD propagation path. The simulation results showed that the ESD protection characteristic of a chip varistors can be improved drastically by reducing the ESD propagation path.

• Journal of IKEEE
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• v.21 no.2
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• pp.150-153
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• 2017

In this paper, a structure of GCNMOS based ESD protection circuit using floating-body technique is proposed. TCAD simulation of Synopsys was used to compare with the conventional GGNMOS and GCNMOS. Compared with the conventional GCNMOS, the proposed ESD protection circuit has lower trigger voltage and faster turn-on-time than conventional circuit because of the added NMOSFET. In the simulation result, the triggering voltage of the proposed ESD protection circuit is 4.86V and the turn-on-time is 1.47ns.

• Journal of IKEEE
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• v.19 no.2
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• pp.265-270
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• 2015

In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.