• 한국멀티미디어학회논문지
• /
• 제10권9호
• /
• pp.1197-1208
• /
• 2007

오늘날 대부분의 스마트카드는 자바카드 플랫폼을 채택한 자바카트가 표준안으로 자리매김 하고 있다. 자바카드 기술은 이식성, 플랫폼 독립성, 높은 보안성 기능을 스마트카드에 제공한다. 그러나 자바카드는 일반 스마트카드에 비해 자바 언어 상의 특성으로 인해 실행속도 저하의 단점을 갖고 있다. 실행속도에 영향을 끼치는 요소는 자바 카드가 데이터를 저장하는 방식과 자바카드 설치기가 애플릿을 설치하는 방식 때문이다. 본 논문에서는 자바카드 프로그램의 적재와 실행의 속도를 개선시키기 위한 방안으로 자바카드에서 EEPROM에 데이터에 대한 저장, 갱신, 삭제하는 과정들을 처리 속도가 빠른 RAM을 이용하여 자바카드의 속도를 개선할 수 있다. 이를 위해 자바카드에서 RAM을 활용한 방법으로 자바카드 환경에 맞는 선반입 LRU-OBL 버퍼 캐쉬 기법을 제시한다. 자바카드에서 생성되는 모든 데이터들을 데이터 특성에 따라 버퍼 캐쉬에서 관리함으로써 EEPROM에 대한 기록 횟수를 최대한 줄여 자바카드의 프로그램 적재 및 실행속도를 향상시킨다.

• 대한전자공학회논문지SD
• /
• 제38권5호
• /
• pp.367-373
• /
• 2001

8개의 N과 P채널 EEPROM을 이용하여 A/D 변환기를 설계하였다. 프로그래밍 모드에서 EEPROM의 선형적 저장능력을 관찰하기 위해 MOSIS의 1.2㎛ double-poly CMOS 공정을 이용하여 셀이 제작되었다. 그 결과 1.25V와 2V구간에서 10㎷ 미만의 오차 내에서 셀이 선형적으로 프로그램 되는 것을 보았다. 이러한 실험 결과를 이용하여 프로그램 가능한 A/D 변환기의 동작이 Hspice에서 시뮤레이션 되었으며, 그 결과 A/D 변환기가 37㎼의 전력을 소모하고 동작주파수는 333㎒ 정도인 것으로 관찰되었다.

• 전자공학회논문지D
• /
• 제34D권9호
• /
• pp.56-63
• /
• 1997

There generally exists a large variation in the thereshold voltages of the flash EEPROM cells after they are erased by using th fowler-nordheim tunneling, thereby getting some cells to be overeased. If the overerased cells are programmed with the conventional one-step programming scheme where an 12-13V pulse with the duration of 100.mu.S is applie don the control gate for the programming, they can suffer from the significant degradation of the reliability of the gate oxide. A two-step programming schem, where an 8/12 V pulse with a duration of 50.mu.S for each voltage is applied on the control gate for the programming, has been studied to solve the problem. The experimental results hav eshown that there is little difference in the programming characteristics between those two schemes, whereas the degradation of the gate oxide due to the programming can be significantly reduced with the two-step programming scheme compared to that with the one-step programming scheme. This is possibly because the positive charge stored in the floating gate of the overerased cells is compensate dwith the electrons injected into the floating gate while the 8V pulse is applied on the control gate, which leaves the overerased cells in the normally erased state after the duration of the 8V pulse.

• 전자공학회논문지A
• /
• 제33A권3호
• /
• pp.107-116
• /
• 1996

Recently, the flash memory has been abstracting great attention in the semiconductor market in the world because of its potential applications as mass storage devices. One of the most significant barriers to the scalling-down of the stacked-gate devices such as EPROM's and flash EEPROM's is the large subthreshold leakage in the unselected cells connected with the bit line of a selected cell in the array during programming. The large subthreshold leakge is majorly due to the capacitive coupling between the floating gates of the unselectd cells and the bit line of selected cell. In this paper, a new programming method to redcue significantly the drain turn-on leakage in the unselected cells during programming has been studied, where a little positive voltage (0.25-0.75V) is applied to the soruce during programming unlike the conventional programming method in which the source is grounded. The resutls of the PISCES simulations and the electrical measurements for the standard EPROM with 0.35.mu.m effective channel length and 1.0.mu.m effective channel width show that the subthreshold leakage in the unselectd cells is significantly large when the source is grounded, whereas it is negligibly small when the source is biased ot a little positive voltage during programming. On the other hadn, the positive bias on the source is found to have little effects on the programming speed of the EPROM.

• E2M - 전기 전자와 첨단 소재
• /
• 제6권4호
• /
• pp.330-338
• /
• 1993

Channel의 폭과 길이가 15 x 15.mu.m, 15 x 1.5.mu.m, 1.9 x 1.7.mu.m인 비휘발성 SNOSFET EEPROM 기억소자를 CMOS 1 Mbit 설계규칙에 의하여 제작하고 체널크기에 따른 $I_{D}$- $V_{G}$특성 및 스위칭 특성을 조사하여 비교하였다. 게아트에 전압을 인가하여 질화막에 전하를 주입시키거나 소거시킨 후 특성을 측정한 결과, 드레인전류가 적게 흐르는 저전도상태와 전류가 많이 흐르는 고전도상태로 되는 것을 확인하였다. 15 x 15.mu.m의 소자는 전형적인 long channel특성을 나타냈으며 15 x 1.5.mu.m, 1.9 x 1.7.mu.m는 short channel특성을 보였다. $I_{D}$- $V_{G}$ 특성에서 소자들의 임계 문턱전압은 저전도상태에서 $V_{W}$=+34V, $t_{W}$=50sec의 전압에서 나타났으며 메모리 윈도우 폭은 15 x 15.mu.m, 15 x 1.5.mu.m, 1.9 x 1.7.mu.m의 소자에서 각각 6.4V, 7.4V, 3.5V였다. 스위칭 특성조사에서 소자들은 모두 논리스윙에 필요한 3.5V 메모리 윈도우를 얻을 수 있었으며 논리회로설계에 적절한 정논리 전도특성을 가졌다.특성을 가졌다.다.다.

• E2M - 전기 전자와 첨단 소재
• /
• 제8권6호
• /
• pp.727-736
• /
• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.

• Transactions on Electrical and Electronic Materials
• /
• 제12권1호
• /
• pp.35-39
• /
• 2011

An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 $\mu$m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 하계학술대회 논문집
• /
• pp.855-858
• /
• 2001

The stress induced leakage currents of thin silicon oxides is investigated in the VLSI implementation of a self learning neural network integrated circuits using a linearity synapse transistor. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 41 ${\AA}$, 86${\AA}$, which have the channel width ${\times}$ length 10 ${\times}$1${\mu}$m, 10 ${\times}$0.3${\mu}$m respectively. The stress induced leakage currents will affect data retention in synapse transistors and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor made by thin silicon oxides has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 하계학술대회 논문집 D
• /
• pp.2634-2636
• /
• 2004

다목적실용위성2호의 위성 본체시스템에는 지상과 연락을 담당하는 주 컴퓨터인 OBC, 위성의 자세를 제어를 위한 원격구동장치인 RDU 그리고 위성의 전원분배를 제어장치인 ECU인 3개의 동일 프로세서(386)가 탑재되어 각 담당 임무를 수행하는 분산형 구조를 갖고 있다. 각 프로세서는 EEPROM과 SRAM 데이터 메모리를 갖고 있는데 전원 리셋이 일어나면 모든 프로그램은 EEPROM에서 SRAM으로 복사되어 운영 프로그램이 실행하도록 되어 있다. 그러나 SRAM은 우주환경에서 위성체는 방사선에 노출되어 손상을 입을 때 SEU이 발생되어 정보가 왜곡되거나 상실되는 문제를 갖고 있다. 그러므로 본 논문에서는 변형된 해밍코드 기법을 이용하여 데이터를 수신하는 곳에서 에러를 검출 및 수정하는 디지털 회로 설계방법을 기술하고자 한다.

• Journal of Electrical Engineering and information Science
• /
• 제2권3호
• /
• pp.132-138
• /
• 1997

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.