• Korean Journal of Optics and Photonics
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• v.24 no.5
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• pp.262-270
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• 2013

In this paper, we propose a modified optical CBC(Cipher Block Chaining) encryption method using optical XOR logic operations. The proposed method is optically implemented by using dual encoding and a free-space interconnected optical logic gate technique in order to process XOR operations in parallel. Also, we suggest a CBC encryption/decryption optical module which can be fabricated with simple optical architecture. The proposed method makes it possible to encrypt and decrypt vast two-dimensional data very quickly due to the fast optical parallel processing property, and provides more security strength than the conventional electronic CBC algorithm because of the longer security key with the two-dimensional array. Computer simulations show that the proposed method is very effective in CBC encryption processing and can be applied to even ECB(Electronic Code Book) mode and CFB(Cipher Feedback Block) mode.

• Transactions on Electrical and Electronic Materials
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• v.6 no.2
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• pp.73-77
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• 2005

In this study, we investigated response characteristics of liquid crystal display (LCD) with different operating mode of nematic liquid crystals (NLCs) such as 45 $^{circ} twisted nematic (TN), 67.3 $^{circ} TN and electrical controlled birefringence (ECB) on the rubbed polyimide (PI) surface with side chains. The pretilt angles generated on polyimide surfaces of the three kinds of LCD operating modes were about 12 $^{circ} that was higher than those of conventional TN-LCOs. Also, the Electro-optical (EO) performance of these LCOs showed stable condition. Low transmittance of the 45 $^{circ} TN and 67.3 $^{circ} TN cell on the rubbed PI surface were measured by using low cell gap d. The fast response time in ECB cell among the three kinds of LCD operating modes was achieved. Also, thermal ability of fast 90 $^{circ} TN-LCD was investigated. The threshold voltage and the response time of thermal stressed TN-LCOs showed the same performances on no thermal stressed TN-LCOs. There was little change of value in these TN cells. However, the transmittances of TN-LCOs on the rubbed PI surface decreased while increasing thermal stress time. Therefore, the thermal stability of TN-LCD was decreased by the high thermal stress for the long duration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.251-253
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• 2019

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.51-61
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• 2008

This paper suggests a new way to implement high speed AES on Intel Core2 processors and AMD Athlon64 processors, which are used all over the world today. First, Core2 Processors of EM64T architecture's memory-access-instruction processing efficiency are lower than calculus-instruction processing efficiency. So, previous AES implementation techniques, which had a high rate of memory-access-instruction, could cause memory-bottleneck. To improve this problem we present the partial round key techniques that reduce the rate of memory-access-instruction. The result in Intel Core2Duo 3.0 Ghz Processors show 185 cycles/block and 2.0 Gbps's throughputs in ECB mode. This is 35 cycles/block faster than bernstein software, which is known for being the fastest way. On the other side, in AMD64 processors of AMD64 architecture, by removing bottlenecks that occur in decoding processing we could improve the speed, with the result that the Athlon64 processor reached 170 cycles/block. The result that we present is the same performance of Matsui's unpublished software.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.261-264
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• 1997

A contactless eddy current type braking system is developed to take advantages of the recent brake system which uses hydraulic force can show high efficiency in a certain velocity region, but not in a high velocity region, and has initial response delay time and pressure build-up time which make stopping distance longer. These are the limits of mechanical brake system of a contact type, which makes a concept brake system required. So, in this paper, the contactless brake system .of a inductive current type is chosen instead of hydraulic brake system. This brake system can be used almost forever for being no wear and contributed to lightening weight of a vehicle. Besides, the contactless brake system can be used as that of electric or solar car with anti-lock brake system. The analysis of induced electromotive force and braking torque obtained with theoretical approximate model, the design of a braking system and a nonlinear controller, and the results of simulation of the ABS, experiment are included.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1019-1020
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• 2011

This paper deals with torque analysis of axial flux permanent magnet (AFPM) type eddy current brake (ECB) based on analytical field computation. On the basis of a magnetic vector potential and a two-dimensional (2-D) polar coordinate system, analytical solutions for normal and tangential flux density due to permanent magnet (PM) considering eddy current effect are obtained. And then, using derived analytical field solutions, braking torque and normal force characteristics according to rotor speed are also predicted. A three-dimensional (3-D) finite element (FE) analysis is employed to confirm the validity of analyses.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1491-1500
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• 2001

본 논문에서는 AES Rijndael 암호 알고리즘을 구현하는 암호 프로세서를 설계하였다. 하드웨어 공유를 통해 면적을 감소시키기 위해 1라운드 동작을 2개의 부분 라운드로 나누고 각 부분 라운드를 4 클록으로 구현하였다. 라운드 당 평균 5 클록의 연산 효율을 만들기 위해 인접한 라운드간에 부분 라운드 라이프라인 동작 기법을 적용하고, 키 설정 오버헤드 시간을 배제하기 위해, 암호 및 복호 동작의 라운드 키를 온라인 계산 기법을 사용하여 생성하였다. 그리고 다양한 응용 분야에 적용하기 위해, 128, 192, 256 비트의 3가지 암호 키를 모두 지원할 수 있도록 하였다. 설계된 암호 프로세서는 약 36,000개의 게이트로 구성되며 0.25$\mu\textrm{m}$ CMOS 공정에서 약 200Mhz의 동작 주파수를 가지며, 키 길이가 128 비트인 AES-128 ECB 동작 모드에서 약 512 Mbps의 암.복호 율의 성능을 얻을 수 있었다.

• Proceedings of the Korea Information Assurance Society Conference
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• 2004.05a
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• pp.59-64
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• 2004

In this paper a design and an implementation of a crypto chip which implements SEED and Triple-DES algorithms are described. We designed it by VHDL(VHSIC Hardware Description Language) which is a designed system-description language. To apply the chip to various application, four operating Modes such as ECB, CBC, CFB, and CFB are supported. The chip was designed by the Virtex-E XCV2000E BG560 of Xilinx and we confirmed result of it at the FPGA implementation by functional and timing simulation using the Xilinx Foundation Series 3.li.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1383-1385
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• 2008

In the viewing-angle image control (VIC) technology, one pixel is made up of a quad pixel structure which is consisting of R, G, B, and electrically control briefringence (ECB) sub-pixels. Two types of test stimuli were used; text & complex image respectively. The limitations of those methods were found from the experiment. From the results the advanced GC technology was proposed.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.1124-1129
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• 2003

In mechanical design, design process is mainly composed of design, explanation and evaluation. In this paper, Using Genetic Algorithms (GA), Evolutionary computation is introduced as new design process. This method promote the efficiency and power of design. Due to the known characteristics of the stage, the approach basically involves a synthetic design method with the composition of building blocks representing the elements of mechanical objects. In order for the building blocks to be more suitable for representation and evolution of mechanical structures, Elementary Cell Blocks (ECBs) are introduced as new building blocks. In this paper, we have demonstrated the implementation of the approach with the design of gear systems.