• Journal of Satellite, Information and Communications
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• v.8 no.3
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• pp.10-14
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• 2013

In this paper, when applying current-mode circuit design technique showing constant power dissipation none the less operation frequency, to the low power design of dynamic voltage frequency scaling, we introduce the low power current-mode circuit design technique applying MOSFET in sub-threshold region, in order to solve the problem that has large power dissipation especially on the condition of low operating frequency. BSIM 3, was used as a MOSFET model in circuit simulation. From the simulation result, the power dissipation of the current memory circuit with sub-threshold MOSFET showed $18.98{\mu}W$, which means the consumption reduction effect of 98%, compared with $900{\mu}W$ in that with strong inversion. It is confirmed that the proposed circuit design technique will be available in DVFS using a current-mode circuit design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9B
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• pp.1082-1091
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• 2011

Power-reduction techniques based on DVFS(Dynamic Voltage and Frequency Scaling) are crucial for lengthening operating times of battery powered mobile systems. This paper proposes an optimal DVFS scheduling algorithm for decoders with memory size limitation on display buffer, which is realistic constraints not properly touched in the previous works. Furthermore, we mathematically prove that the proposed algorithm is optimal in the limited display buffer and limited clock frequency model, and also can be used for feasibility check. Simulation results show the proposed algorithm outperformed the previous heuristic algorithms by 7% in average, and the performance of all algorithms using display buffers saturates at about 10 frame size.

• Journal of the Korean Geotechnical Society
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• v.23 no.3
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• pp.141-147
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• 2007

Various approaches have been developed for the dynamic response analysis of piles. In one of the approaches, the soil-pile interaction is approximated by using parallel nonlinear springs, namely the p-y curves. Currently available p-y curve recommendations are based on static and cyclic lateral load tests. Other researchers have attempted to extend the p-y curves by incorporating the effects of liquefaction on soil-pile interaction and derived scaling factors of p-y curves to account fur the liquefaction. However, opinions on the scaling factors vary. In this study, the sealing factors, which reflect the variation of the elastic moduli of surrounding soils, were established combining the relationship between excess pore pressures and the natural frequencies of a soil-pile system obtained from Ig shaking table tests and the relationship between the elastic moduli of surrounding soils and the natural frequencies of a soil-pile system obtained from numerical analyses. As a result, the scaling factors were presented in an exponential function.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1379-1382
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• 2003

Recently, mobile embedded systems used widly in various applications. Managing power consumption is becoming a matter of primary concern because those systems use limited power supply. As an approach reduce power consumption, voltage can be scaled down. according to the execution time and deadline. By reducing the supplying voltage to 1/N power consumption can be reduced to 1/N. DPM-S is a well known method for dynamic voltage scaling. In this paper, we enhanced DPM-S by using average execution time aggressively. The frequency of processor is calculated based in average execution time instead of worst case execution time. Simulation results show that our method achieve up to 5％ energy savings than DPM-S.

• Journal of Information Processing Systems
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• v.5 no.4
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• pp.175-186
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• 2009

Power consumed by modern computer systems, particularly servers in data centers has almost reached an unacceptable level. However, their energy consumption is often not justifiable when their utilization is considered; that is, they tend to consume more energy than needed for their computing related jobs. Task scheduling in distributed computing systems (DCSs) can play a crucial role in increasing utilization; this will lead to the reduction in energy consumption. In this paper, we address the problem of scheduling precedence-constrained parallel applications in DCSs, and present two energy- conscious scheduling algorithms. Our scheduling algorithms adopt dynamic voltage and frequency scaling (DVFS) to minimize energy consumption. DVFS, as an efficient power management technology, has been increasingly integrated into many recent commodity processors. DVFS enables these processors to operate with different voltage supply levels at the expense of sacrificing clock frequencies. In the context of scheduling, this multiple voltage facility implies that there is a trade-off between the quality of schedules and energy consumption. Our algorithms effectively balance these two performance goals using a novel objective function and its variant, which take into account both goals; this claim is verified by the results obtained from our extensive comparative evaluation study.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.142-147
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• 2012

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${\mu}m$ CMOS process. The measured duty cycle error is less than ${\pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.854-857
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• 2015

As the number of devices integrated on system-on-chip(SoC) increases exponentially, energy reduction technology is essential. Dynamic Voltage and Frequency Scaling (DVFS) is a very effective technique for reducing power consumption. Since it requires complex voltage regulators and PLL circuits, DVFS tends to have significant overheads. In this paper, we propose a new voltage selection algorithm to minimize transition overhead for multiprocessor SoC (MPSoC). Simulation results show that proposed algorithm appears less energy consumption with transition overhead even though maintains performance.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.423-430
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• 2012

An adaptive maximum power point tracking (MPPT) scheme employing a variable scaling factor is presented. A MPPT control loop was constructed analytically and the magnitude variation in the MPPT loop gain according to the operating point of the PV array was identified due to the nonlinear characteristics of the PV array output. To make the crossover frequency of the MPPT loop gain consistent, the variable scaling factor was determined using an approximate curve-fitted polynomial equation about linear expression of the error. Therefore, a desirable dynamic response and the stability of the MPPT scheme were maintained across the entire MPPT voltage range. The simulation and experimental results obtained from a 3 KW rated prototype demonstrated the effectiveness of the proposed MPPT scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.9
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• pp.1405-1411
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• 2022

Power management is still an important issue in embedded environments as hardware advances like high-performance processors. Power management methods such as DVFS control CPU frequencies in an adaptive manner for efficient power management in polling-based I/O programs such as network communication. This paper presents the problems of the existing power management method and proposes a new power management method. Through this, it is possible to reduce electric consumption by increasing the polling cycle in situations where the frequency of data reception is low, and on the contrary, in situations where data reception is frequent, it can operate at the maximum frequency without performance degradation. After implementing this as a code layer on the embedded board and observing it through Atmel's Power Debugger, the proposed method showed a performance improvement of up to 30% in energy consumption compared to the existing power management method.

• Korea-Australia Rheology Journal
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• v.20 no.1
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• pp.27-34
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• 2008

Clay suspensions in liquid polymers exhibit a time-dependent behaviour that includes viscoelastic as well as thixotropic features. Because of the presence of interacting clay platelets, particulate networks can develop, which are broken down during flow and rebuild upon cessation of the flow. Here, the use of thixotropic techniques in probing flow-induced structures in nanocomposites is explored with data on a hectorite-poly(isobutylene) model system. By means of fast stress jump measurements the hydrodynamic contributions to the steady state stresses are determined as well as those caused by the stretching of the clay floes. Flow reversal measurements do not provide a clear indication of flow-induced anisotropy in the present case. The recovery of the clay microstructure upon cessation of flow is followed by means of overshoot and dynamic measurements. The development of a particulate network is detected by the appearance and growth of a low frequency plateau of the storage moduli. The modulus-frequency curves after various rest times collapse onto universal master curves, regardless of the pre-shear history or temperature. The scaling factors for this master curve are the crossover parameters. The crossover moduli are nearly a linear function of the crossover frequency, the relation being identical for recovery after shearing at different shear rates. This function depends, however, on temperature.