• Journal of electromagnetic engineering and science
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• v.14 no.2
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• pp.61-67
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• 2014

This paper presents a zero-IF CMOS RF receiver, which supports three channel bandwidths of 5/10/40MHz for LTE-Advanced systems. The receiver operates at IMT-band of 2,500 to 2,690MHz. The simulated noise figure of the overall receiver is 1.6 dB at 7MHz (7.5 dB at 7.5 kHz). The receiver is composed of two parts: an RF front-end and a baseband circuit. In the RF front-end, a RF input signal is amplified by a low noise amplifier and $G_m$ with configurable gain steps (41/35/29/23 dB) with optimized noise and linearity performances for a wide dynamic range. The proposed baseband circuit provides a -1 dB cutoff frequency of up to 40MHz using a proposed wideband OP-amp, which has a phase margin of $77^{\circ}$ and an unit-gain bandwidth of 2.04 GHz. The proposed zero-IF CMOS RF receiver has been implemented in $0.13-{\mu}m$ CMOS technology and consumes 116 (for high gain mode)/106 (for low gain mode) mA from a 1.2 V supply voltage. The measurement of a fabricated chip for a 10-MHz 3G LTE input signal with 16-QAM shows more than 8.3 dB of minimum signal-to-noise ratio, while receiving the input channel power from -88 to -12 dBm.

• Journal of the Korean Solar Energy Society
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• v.37 no.3
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• pp.47-59
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• 2017

As the global warming threats to humanity, renewable energy is considered the key solution to overcome the climate change. In this circumstance, distributed PV systems are being expanded significantly its market share in the renewable energy industry. The performance of inverter is the most important component at PV system and numerous researches are focusing on it. In order to improve the inverter, PV simulator is an essential device to experiment under various load and conditions. This paper proposes the PV Power-Hardware-In-Loop simulator (PHILS) with real-time processing converted electrical and mathematical models to improve computation speed. Single-diode PV model is used in MATLAB/SIMULINK for the PV PHILS to boosting computation speed and dynamic model accuracy. In addition, control algorithms for sub-components such as DC amplifier, measurement device and several interface functions are implemented in the model. The proposed PV PHILS is validated by means of experiments with commercial PV module parameters.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.3
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• pp.278-284
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• 2010

In this paper, a millimeter-wave detector using zero-bias schottky diode is designed and fabricated at W-band. It consists of LNA(Low Noise Amplifier) and detector module to improve sensitivity. LNA case with a highly stop-band characteristic is designed to prevent the oscillation by LNA MMIC chip. Diode detector of planar structure is fabricated for the easy connection with LNA module and zero bias Schottky diode is utilized. In practice, the fabricated diode detector have shown the detection voltage of 20~500 mV to the RF input power of -45~-20 dBm. The proposed W-band detector can be applicable to the passive millimeter image system.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• The Journal of Korean Academy of Prosthodontics
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• v.39 no.6
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• pp.709-734
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• 2001

The aims of this experiment were to investigate the strain and temperature changes simultaneously within autopolymerzing acrylic resin specimens. A computerized data acquisition system with an electrical resistance strain gauge and a thermocouple was used over time periods up to 180 minutes. The overall strain kinetics, the effects of stress relaxation and additional heat supply during the polymerization were evaluated. Stone mold replicas with an inner butt-joint rectangular cavity ($40.0{\times}25.0mm$, 5.0mm in depth) were duplicated from a brass master mold. A strain gauge (AE-11-S50N-120-EC, CAS Inc., Korea) and a thermocouple were installed within the cavity, which had been connected to a personal computer and a precision signal conditioning amplifier (DA1600 Dynamic Strain Amplifier, CAS Inc., Korea) so that real-time recordings of both polymerization-induced strain and temperature changes were performed. After each of fresh resin mixture was poured into the mold replica, data recording was done up to 180 minutes with three-second interval. Each of two poly(methyl methacrylate) products (Duralay, Vertex) and a vinyl ethyl methacrylate product (Snap) was examined repeatedly ten times. Additionally, removal procedures were done after 15, 30 and 60 minutes from the start of mixing to evaluate the effect of stress relaxation after deflasking. Six specimens for each of nine conditions were examined. After removal from the mold, the specimen continued bench-curing up to 180 minutes. Using a waterbath (Hanau Junior Curing Unit, Model No.76-0, Teledyne Hanau, New York, U.S.A.) with its temperature control maintained at $50^{\circ}C$, heat-soaking procedures with two different durations (15 and 45 minutes) were done to evaluate the effect of additional heat supply on the strain and temperature changes within the specimen during the polymerization. Five specimens for each of six conditions were examined. Within the parameters of this study the following results were drawn: 1. The mean shrinkage strains reached $-3095{\mu}{\epsilon},\;-1796{\mu}{\epsilon}$ and $-2959{\mu}{\epsilon}$ for Duralay, Snap and Vertex, respectively. The mean maximum temperature rise reached $56.7^{\circ}C,\;41.3^{\circ}C$ and $56.1^{\circ}C$ for Duralay, Snap, and Vertex, respectively. A vinyl ethyl methacrylate product (Snap) showed significantly less polymerization shrinkage strain (p<0.01) and significantly lower maximum temperature rise (p<0.01) than the other two poly(methyl methacrylate) products (Duralay, Vertex). 2. Mean maximum shrinkage rate for each resin was calculated to $-31.8{\mu}{\epsilon}/sec,\;-15.9{\mu}{\epsilon}/sec$ and $-31.8{\mu}{\epsilon}/sec$ for Duralay, Snap and Vertex, respectively. Snap showed significantly lower maximum shrinkage rate than Duralay and Vertex (p<0.01). 3. From the second experiment, some expansion was observed immediately after removal of specimen from the mold, and the amount of expansion increased as the removal time was delayed. For each removal time, Snap showed significantly less strain changes than the other two poly(methyl methacrylate) products (p<0.05). 4. During the external heat supply for the resins, higher maximum temperature rises were found. Meanwhile, the maximum shrinkage rates were not different from those of room temperature polymerizations. 5. From the third experiment, the external heat supply for the resins during polymerization could temporarily decrease or even reverse shrinkage strains of each material. But, shrinkage re-occurred in the linear nature after completion of heat supply. 6. Linear thermal expansion coefficients obtained from the end of heat supply continuing for an additional 5 minutes, showed that Snap exhibited significantly lower values than the other two poly(methyl methacrylate) products (p<0.01). Moreover, little difference was found between the mean linear thermal expansion coefficients obtained from two different heating durations (p>0.05).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.47-54
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• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

• Journal of Biomedical Engineering Research
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• v.25 no.4
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• pp.269-275
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• 2004

Different biological tissues have different values of electrical resistivity. In EIT (electrical impedance tomography), we try to provide cross-sectional images of a resistivity distribution inside an electrically conducting subject such as the human body mainly for functional imaging. However, it is well known that the image reconstruction problem in EIT is ill-posed and the quality of a reconstructed image highly depends on the measurement error. This requires us to develop a high-performance EIT system. In this paper, we describe the development of a 16-channel digital EIT system including a single constant current source, 16 voltmeters, main controller, and PC. The system was designed and implemented using the FPGA-based digital technology. The current source injects 50KHz sinusoidal current with the THD (total harmonic distortion) of 0.0029% and amplitude stability of 0.022%. The single current source and switching circuit reduce the measurement error associated with imperfect matching of multiple current sources at the expense of a reduced data acquisition time. The digital voltmeter measuring the induced boundary voltage consists of a differential amplifier, ADC, and FPGA (field programmable gate array). The digital phase-sensitive demodulation technique was implemented in the voltmeter to maximize the SNR (signal-to-noise ratio). Experimental results of 16-channel digital voltmeters showed the SNR of 90dB. We used the developed EIT system to reconstruct resistivity images of a saline phantom containing banana objects. Based on the results, we suggest future improvements for a 64-channel muff-frequency EIT system for three-dimensional dynamic imaging of bio-impedance distributions inside the human body.

• The Journal of Korean Academy of Prosthodontics
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• v.45 no.6
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• pp.717-723
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• 2007

Statement of problem. Unreasonable distal cantilevered implant-supported prosthesis can mask functional problems of reconstruction temporarily, but it can cause serious strain and stress around its supported implant and surrounding alveolar bone. Purpose. The purpose of this study was to evaluate strain of implants supporting distal cantilevered fixed prosthesis with two different cantilevered length under distal cantilevered static load. Material and methods. A partially edentulous mandibular test model was fabricated with auto-polymerizing resin (POLYUROCK; Metalor technologies, Stuttgart, Swiss) and artificial denture teeth (Endura; Shofu inc., Kyoto, Japan). Two implants-supported 5-unit screw-retained cantilevered fixed prosthesis was made using standard methods with Type III gold alloy (Harmony C&B55; Ivoclar-vivadent, Liechtenstein, Germany) for superstructure and reinforced hard resin (Tescera; Ivoclar-vivadent, Liechtenstein, Germany) for occlusal material. Two strain gauges (KFG-1-120-C1-11L1M2R; KYOWA electronic instruments, Tokyo, Japan) were then attached to the mesial and the distal surface of each standard abutment with adhesive (M-bond 200; Tokuyama, Tokyo, Japan). Total four strain gauges were attached to test model and connected to dynamic signal conditioning strain amplifier (CTA1000; Curiotech inc., Paju, Korea). The stepped $20{\sim}100$ N in 25 N increments, cantilevered static load 8mm apart (Group I) or 16mm apart (Group II), were applied using digital push-pull gauge (Push-Pull Scale & Digital Force Gauge, Axis inc., Seoul, Korea). Each step was performed ten times and every strain signal was monitored and recorded. Results. In case of Group I, the strain values were surveyed by $80.7{\sim}353.8{\mu}m$ in Ch1, $7.5{\sim}47.9{\mu}m/m$ in Ch2, $45.7{\sim}278.6{\mu}m/m$ in Ch3 and $-212.2{\sim}718.7{\mu}m/m$ in Ch4 depending on increasing cantilevered static load. On the other hand, the strain values of Group II were surveyed by $149.9{\sim}612.8{\mu}m/m$ in Ch1, $26.0{\sim}168.5{\mu}m/m$ in Ch2, $114.3{\sim}632.3{\mu}m/m$ in Ch3, and $-323.2{\sim}-894.7{\mu}m/m$ in Ch4. Conclusion. A comparative statistical analysis using paired sample t-test about Group I Vs Group II under distal cantilevered load shows that there are statistical significant differences for all 4 channels (P<0.05).

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.2
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• pp.58-67
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• 1995

The paper describes the variation of magnetic fields caused by the operation of induction motors. The measuring system consists of the self-integrating magnetic field sensor, amplifier, and active integrator. From the calibration experiments, the frequency bandwidth of the magnetic field measuring system ranges from 20[Hz] to 300[kHz] and sensitivity is 0.234(mV/$\mu\textrm{T}$]. The magnetic fields generated under steady state and starting operations of duction motor are recorded by the proposed measuring system, and the fast Fourier transformation(FFT) of the measured data is performed to analyze the harmonic components. A single pulsed magnetic field is strongly caused by direct starting the induction motor, and its peak value is greater than 5 times as compared with the steady state value. The long transient duration and high intensity originates from the large inductance and dynamic characteristic of the induction motor, During the steady state operation of induction motor, subharmonics of magnetic field components, which depend on the pole number of induction motor, are observed. The lower order power-line harmonics can be inferred from the voltage flicker and current ripple which are derived from the torque fluctuation of induction motor. In the case of the induction motor drived by inverter, the harmonics of magnetic field are much more than those caused by direct starting method and are found generally to increase with decreasing the driving frequency.