• The Transactions of the Korean Institute of Power Electronics
• /
• v.5 no.4
• /
• pp.386-393
• /
• 2000

This paper presents an improved ZVS partial series resonant DC/DC converter (PSRC) with low conduction losses, suitable for high power and high frequency applications. The proposed PSRC have advantages of zero-voltage-switching (ZVS) of main switches for entire load ranges low conduction losses of main switches by decreasing current stresses. Also the reduction of the effective duty cycle is not occurred during the resonant period of the main circuit because the auxiliary circuit of the proposed converter is placed out of the main power path. The auxiliary circuit is composed with passive components, which are an inductor, two capacitors, two diodes, and a saturable inductor. An improved ZVS PSRC has so much characteristics with respect to the overall system efficiency and to the reduction of current stresses. The operation principles of the proposed converter are explained in detail and the various simulated and experimental results show the validity of the proposed converter.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.14 no.1
• /
• pp.23-30
• /
• 2009

A new high performance and low cost unified power system is proposed through investigating conventional Power-Integrated Drive(PID) system and Power-Separated Drive(PSD) system applied to LCD TV. Since the proposed system consists of two stage, namely power and inverter stage it features high efficiency and cost effectiveness. To satisfy the safety standard of the High voltage transformer, 1:1 transformer is employed between inverter and high voltage transformer. Moreover, to ensure the Zero Voltage Switching(ZVS) of all power switches and the Pulse Count Modulation(PCM) method is employed, which controls the number of pulse at the fixed frequency and fixed duty cycle. Therefore, it features high efficiency, improved heat generation, cost effectiveness and good EMI performance including no additional current balancing coil. To confirm the validity of proposed system, comparison of conventional system, verification of experimental results are presented.

• Journal of Power Electronics
• /
• v.14 no.1
• /
• pp.30-39
• /
• 2014

This paper studies a new three-level pulse-width modulation (PWM) resonant converter for high input voltage and high load current applications. In order to use high frequency power MOSFETs for high input voltage applications, a three-level DC converter with two clamped diodes and a flying capacitor is adopted in the proposed circuit. For high load current applications, the secondary sides of the proposed converter are connected in parallel to reduce the size of the magnetic core and copper windings and to decrease the current rating of the rectifier diodes. In order to share the load current and reduce the switch counts, three resonant converters with the same active switches are adopted in the proposed circuit. Two transformers with a series connection in the primary side and a parallel connection in the secondary side are adopted in each converter to balance the secondary side currents. To overcome the drawback of a wide range of switching frequencies in conventional series resonant converters, the duty cycle control is adopted in the proposed circuit to achieve zero current switching (ZCS) turn-off for the rectifier diodes and zero voltage switching (ZVS) turn-on for the active switches. Finally, experimental results are provided to verify the effectiveness of the proposed converter.

• Journal of Advanced Marine Engineering and Technology
• /
• v.36 no.6
• /
• pp.844-849
• /
• 2012

In this paper, a bidirectional Zeta-Flyback converter is proposed. The topology of the proposed converter is analyzed, which is superposition of bidirectional Flyback converter mode and bidirectional Zeta converter mode in a cycle. The proposed converter allows power flow in either a forward direction or a backward direction. Bidirectional power flow is obtained by a transformer and components. The proposed converter's output is controlled by duty of constant frequency PWM of switch. Compared to conventional bidirectional isolated DC-DC converters, the proposed isolated bidirectional DC-DC converter has high power density and high transformer utilization. To confirm the proposed converter, the simulation and experimental results are presented.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.23 no.9
• /
• pp.1079-1086
• /
• 2012

In this paper, X-band 60 W Solid-State Power Amplifier with sequential control circuit and pulse width variation circuit for improve bias of SSPA module was designed. The sequential control circuit operate in regular sequence drain bias switching of GaAs FET. The distortion and efficiency of output signals due to SSPA nonlinear degradation is increased by making operate in regular sequence the drain bias wider than that of RF input signals pulse width if only input signal using pulsed width variation. The GaAs FETs are used for the 60 W SSPA module which is consists of 3-stage modules, pre-amplifier stage, driver-amplifier stage and main-power amplifier stage. The main power amplifier stage is implemented with the power combiner, as a balanced amplifier structure, to obtain the power greater than 60 W. The designed SSPA modules has 50 dB gain, pulse period 1 msec, pulse width 100 us, 10 % duty cycle and 60 watts output power in the frequency range of 9.2~9.6 GHz and it can be applied to solid-state pulse compression radar using pulse SSPA.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.17 no.2
• /
• pp.73-80
• /
• 2003

This Paper Proposes instantaneous following control method to control pulse modulation switching converter by using principle that reset time of integrator is inverse proportion in size of integrator input voltage. proposed control method acts of fixed frequency and control switch calculates time of become turn on and turn off using analog integrator. Duty ratio that express switching time of converter is depended on mean value of switching variable and following time consists in one cycle. Follow to do order exactly stationary state as well as transition state, and controller corrects mean value of control variable and control reference value and control as control error gets into zero. Proposed control method could experimented and know that experiment result and theory are agreeing well through this using the buck converter.

• Journal of Biomedical Engineering Research
• /
• v.43 no.1
• /
• pp.1-10
• /
• 2022

Non-alcoholic fatty liver disease(NAFLD) is excessive hepatic lipid accumulation mainly caused by obesity. This study aimed to evaluate whether micro-current stimulation(MCS) could modulate lipid metabolism regarding the Sirt1/AMPK pathway, fatty acid β-oxidation pathway, and lipolysis and lipogenesis-related factors in FL83B cells. For the NAFLD cell model, FL83B cells were treated with oleic acid for lipid accumulation. MCS were stimulated for 1 hr and used frequency 10 Hz, duty cycle 50%, and biphasic rectangular current pulse. The intensity of MCS was divided into 50, 100, 200, and 400 ㎂. Through the results of Oil red O staining, it was confirmed that MCSs with the intensity of 200 ㎂ and 400 ㎂ significantly reduced the degree of lipid droplet formation. Thus, these MCS intensities were applied to western blot analysis. Western blot analysis was performed to analyze the effects of MCS on lipid metabolism. MCS with the intensity of 400 ㎂ showed that significantly activated the Sirt1/AMPK pathway, a key pathway for regulating lipid metabolism in hepatocytes, and fatty acid β-oxidation-related transcription factors. Moreover, it activated the lipolysis pathway and suppressed lipogenesis-related transcription factors such as SREBP-1c, FAS, and PPARγ. In the case of MCS with the intensity of 200 ㎂, only PGC1α and SREBP-1c showed significant differences compared to cells treated only with oleic acid. Taken together, these results suggested that MCS with the intensity of 400 ㎂ could alleviate hepatic lipid accumulation by modulating lipid metabolism in hepatocytes.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.4
• /
• pp.39-50
• /
• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.