• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1C
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• pp.1-8
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• 2005

In this paper, we present a novel LDPC code construction called as semi-algebra low density parity check(LDPC) codes which is one kind of deterministic LDPC code based on dual-diagonal sub-matrix. The constructing method results in a class of high rate LDPC codes. Codes in this class have a large girth and good minimum distances. Furthermore, they can be implemented by simple parallel array architecture using cyclic shift register and perform well with the iterative decoding.

• Journal of Institute of Control, Robotics and Systems
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• v.4 no.2
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• pp.264-272
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• 1998

This paper proposes a fault detection and recovery mechanism for a fault-tolerant Mini-MAP system, and provides detailed techniques for its implementation. This paper considers the fault-tolerant Mini-MAP system which has dual layer structure from the LLC sublayer down to the physical layer to cope with the faults of those layers. For a good fault detection, a redundant and hierarchical fault supervision architecture is proposed and its implementation technique for a stable detection operation is provided. Information for the fault location is provided from data reported with a fault detection and obtained by an additional network diagnosis. The faults are recovered by the stand-by sparing method applied for a dual network composed of two equivalent networks. A network switch mechanism is proposed to achieve a reliable and stable network function. A fault-tolerant Mini-MAP system is implemented by applying the proposed fault detection and recovery mechanism.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.287-290
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• 2002

This paper rotates to tile FPGA that is reffered to as the UTOSPI. The design goal of the FPGA is to convert the UTOPIA-3 bus interface to the SPI-3 bus interface, so that the SAR chips on the ATM interface board can be interfaced to the packet processor through this FPGA. We Propose a new architecture that has two Dual Port RAMs and flow control signals. To buffer data, the UTOSPI has a Dual port RAM in the receive direction and the same size of that in the transmit direction. This design has been implemented, compiled, and tested using a Xilinx Virtex-I XCV-300E FPGA.

• Journal of electromagnetic engineering and science
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• v.8 no.1
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• pp.34-39
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• 2008

An RF front-end dual-conversion receiver for $3{\sim}5\;GHz$ MB-OFDM UWB systems is implemented in $0.18\;{\mu}m$ CMOS technology. The receiver includes a two-stage UWB LNA, an RF mixer, an IF I/Q mixer, and a frequency synthesizer. The proposed receiver adopts the dual-conversion architecture to mitigate the burden of design of the frequency synthesizer. Accordingly, the proposed frequency synthesizer generates four LO tones from only one VCO. The receiver front-end achieves power gain of 16.3 to 21 dB, NF of 7 to 7.6 dB over $3{\sim}5\;GHz$, and IIP3 of -21 dBm, while consuming 190 mW from a 1.8 V supply.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2002.10a
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• pp.94-99
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• 2002

최근 들어 해양개발에 관심이 고조되면서 심해저의 진출이 늘어날 것으로 보이며 또한 환경에 미치는 영향 등으로 부유식 소파제의 이용이 늘어날 것으로 생각된다. 이러한 부유식 소파제는 고정식 방파제의 문제점을 상당히 해소할 수 있는 반면 아직까지 완전히 이해되고 해결되지 못한 부정적인 면도 가지고 있다. 이에 본 연구는 부유식 소파제의 설계시 이용 가능한 정보를 얻고자 부유식 소파제의 형상과 파수에 따른 투과율에 대해 원형과 사각형 그리고 catamaran을 비교하였으며 사각형에 있어서는 계류삭의 위치에 따른 차이점을 비교하였다. 또한 catamaran 부소 파제의 후면에 catamaran 구조물이 있는 경우 즉, Dual catamaran의 운동에 대해서도 고찰하였다.

• Journal of the Korea Institute of Military Science and Technology
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• v.18 no.4
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• pp.415-422
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• 2015

The flow field structures of dual jet-in-cross-flow were examined experimentally for in-lined perforated damage holes configuration using particle image velocimetry. Ensemble averaged in-plane velocity and vorticity data in the jet were determined to study the mean jet structure. Jets are formed by pressure differences between upper and lower airfoil surface. The flow structure of vicinity of the thru holes consist of a vortical structure that wrap around the jets like a horseshoe and develop further downstream through a pair of stream-wise vortices. The shape, size and location of the horseshoe vortex were found to be dependent on the angle of attack. In spite of the existence of battle damage holes, the effect on the control force was insignificant when the damage size was not large enough.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.535-537
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• 2004

최근의 멀티미디어 시스템 설계 (예: 휴대폰, PDA) 경향에서 전력 소모를 줄이는 연구가 매우 긴요한 상황에, 본 연구는 누설 전류(leakage power)를 줄이는 연산 회로 아키텍쳐 합성 기법을 제안한다. 누설 전류를 줄이기 위한 방법으로 본 연구는 Dual threshold Voltage (Dual-V$_{T}$) 기법을 적용한다. 기존의 연구에서는 회로 설계 단계 중 논리나 트랜지스터 수준에서DUal-V$_{T}$를 적용한 방법과는 달리, 보다 상위 단계인 회로의 아키텍쳐 합성 단계에서의 지연시간 제약 조건을 만족하는 범위에서 최소의 누설전류 소모를 위한 합성 기법을 제안한다 따라서, 지연 시간과 누설전류 간의 Trade-Off를 이용하여 설계 조건에 맞는 융통성 있는 설계 결과를 얻을 수 있는 장점을 제공한다. 본 연구는 케리-세이브 가산기 (Carry-Save Adder) 모듈의 생성 과정에 국한된 합성 알고리즘의 적용을 보이고 있지만, 일반적인 연산 모듈을 사용한 아키텍쳐 설계 과정에서도 본 알고리즘을 쉽게 변형, 적용할 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.75-82
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• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.31 no.3
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• pp.133-140
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• 2018

This paper is concerned with the 2-D micostructure generation for $Ni-A{\ell}_2O_3$ dual-phase composite materials and the numerical analysis of mechanical characteristic of hierarchical models of microstructure which are defined in terms of the scale of microstructure. The microstructures of dual-phase composite materials were generated by applying the mathematical RMDF(random morphology description functions) technique to a 2-D RVE of composite materials. And, the hierarchical models of microstructure were defined by the number of Gaussian points. Meanwhile, the volume fractions of metal and ceramic particles were set by adjusting the level of RMD functions. The microstructures which were generated by RMDF technique are definitely random even though the total number of Gaussian points is the same. The randomly generated microstructures were applied to a 2-D beam model, and the variation of normal and shear stresses to the scale of microstructure was numerically investigated. In addition, through the crack analyses, the influence of RMDF randomness and Gauss point number on the crack-tip stress is investigated.

• Journal of the Korea Institute of Military Science and Technology
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• v.23 no.6
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• pp.639-649
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• 2020

Air data systems measure airspeed, pressure altitude, angle of attack and angle of sideslip. These measurements are essential for operating flight control laws to ensure safe flights. Since the loss or corruption of air data measurements is considered as catastrophic, a high level of operational reliability needs to be achieved for air data systems. In the case of unmanned air vehicles, failure of any of air data sensors is more critical due to the absence of onboard pilot decision aid. This paper presents design of a dual redundancy air data system and the integration process for an unmanned air vehicle. The proposed dual-redundant architecture is based on two independent air data probes and redundancy management by central processing in two independent flight control computers. Starting from unit testing of single air data sensor, details are provided of system level tests used to meet overall requirements. Test results from system integration demonstrate the efficiency of the proposed process.