• Bulletin of the Korean Mathematical Society
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• v.60 no.3
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• pp.829-844
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• 2023

In this paper, we present a new construction for self-dual codes that uses the concept of double bordered construction, group rings, and reverse circulant matrices. Using groups of orders 2, 3, 4, and 5, and by applying the construction over the binary field and the ring F₂ + uF₂, we obtain extremal binary self-dual codes of various lengths: 12, 16, 20, 24, 32, 40, and 48. In particular, we show the significance of this new construction by constructing the unique Extended Binary Golay Code [24, 12, 8] and the unique Extended Quadratic Residue [48, 24, 12] Type II linear block code. Moreover, we strengthen the existing relationship between units and non-units with the self-dual codes presented in [10] by limiting the conditions given in the corollary. Additionally, we establish a relationship between idempotent and self-dual codes, which is done for the first time in the literature.

• Nuclear Engineering and Technology
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• v.41 no.8
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• pp.1005-1014
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• 2009

The Dual Unit Optimizer 2000 MWe (DUO2000) is put forward as a new design concept for large power nuclear plants to cope with economic and safety challenges facing the $21^{st}$ century green and sustainable energy industry. DUO2000 is home to two nuclear steam supply systems (NSSSs) of the Optimized Power Reactor 1000 MWe (OPR1000)-like pressurized water reactor (PWR) in single containment so as to double the capacity of the plant. The idea behind DUO may as well be extended to combining any number of NSSSs of PWRs or pressurized heavy water reactors (PHWRs), or even boiling water reactors (BWRs). Once proven in water reactors, the technology may even be expanded to gas cooled, liquid metal cooled, and molten salt cooled reactors. With its in-vessel retention external reactor vessel cooling (IVR-ERVC) as severe accident management strategy, DUO can not only put the single most querulous PWR safety issue to an end, but also pave the way to very promising large power capacity while dispensing with the huge redesigning cost for Generation III+ nuclear systems. Five prototypes are presented for the DUO2000, and their respective advantages and drawbacks are considered. The strengths include, but are not necessarily limited to, reducing the cost of construction by decreasing the number of containment buildings from two to one, minimizing the cost of NSSS and control systems by sharing between the dual units, and lessening the maintenance cost by uniting the NSSS, just to name the few. The latent threats are discussed as well.

• Transactions of The Korea Fluid Power Systems Society
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• v.8 no.3
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• pp.14-20
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• 2011

This study aims at aligning multiple wafers to reduce wafer handling time in wafer processes. We designed a multilevel structure for a prealigner which can handle multiple wafer simultaneously in a system. The system consists of gripping parts, kinematic parts, vacuum chucks, pneumatic units, hall sensors and a DSP controller. Aligning procedure has two steps: mechanical gripping and notch finding. In the first step, a wafer is aligned in XY directions using 4-point mechanical contact. The rotational error can be found by detecting a signal in a notch using hall sensors. A dual prealigner was designed for 300mm wafers and constructed for a performance test. The accuracy was monitored by checking the movement of a notch in a machine vision. The result shows that the dual prealigner has enough performance as commercial products.

• Journal of Power Electronics
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• v.12 no.6
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• pp.886-894
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• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.1
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• pp.97-115
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• 2022

Smart power grid is a user friendly system that transforms the traditional electric grid to the one that operates in a co-operative and reliable manner. Demand Response (DR) is one of the important components of the smart grid. The DR programs enable the end user participation by which they can communicate with the electricity service provider and shape their daily energy consumption patterns and reduce their consumption costs. The increasing demands of electricity owing to growing population stresses the need for optimal usage of electricity and also to look out alternative and cheap renewable sources of electricity. The solar and wind energy are the promising sources of alternative energy at present because of renewable nature and low cost implementation. The proposed work models a smart home with renewable energy units. The random nature of the renewable sources like wind and solar energy brings an uncertainty to the model developed. A stochastic dual descent optimization method is used to bring optimality to the developed model. The proposed work is validated using the simulation results. From the results it is concluded that proposed work brings a balanced usage of the grid power and the renewable energy units. The work also optimizes the daily consumption pattern thereby reducing the consumption cost for the end users of electricity.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.11
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• pp.635-644
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• 2002

Many generating units can be in parallel connection to one battery and inverter. However, one of the biggest problems we encountered is that wind speed is fluctuated sharply in accordance with the unstable weather conditions. To solve this problem, we need energy storage equipment such as storage lead-acid battery. We design a system and analyze its modeling so that it supplies a stable power to the load through DC-AC inverter part. In this paper, we applied dual step-up/down buck-boost converter and dual high-frequency half-bridge converter to the proposed system. These converters are used to store energy in the battery regardless of the change of the wind speed. The operation process of two proposed types of converters for high-power battery charging is discussed along with simulation and experimental result. We design a charging circuit which is applicable in the actual wind power generation system for 30kw and confirm the circuit's validity.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.23-30
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• 2006

This paper presents design andd verification of a circuit that improves the control-operation problems of Stored Program Optical Computer (SPOC), which is an optical computer using $LiNbO_3$ optical switching element. Since the memory of SPOC takes the Delay Line Memory (DLM) architecture and instructions that are needless of operands should go though memory access stages, SPOC memory have problems; it takes immoderate access time and unnecessary operations are executed in Arithmetic Logical Unit (ALU) because desired operations can't be selectively executed. In this paper, improvement on circuit has been achieved by removing the memory access of instructions that are needless of operands by decoding instructions before locating operand. Unnecessary operations have been reduced by sending operands to some specific operational units, not to all the operational units in ALD. We show that total execution time of a program is minimized by using the Dual Instruction Register(DIR) architecture.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.7
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• pp.231-240
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• 2014

Video transcoding techniques provide an efficient mechanism to make a video content adaptive to the capabilities of a variety of clients. However, it is hard to provide an appropriate quality-of-service(QoS) to the clients owing to heavy workload on transcoding operations. In light of this fact, this paper presents the dual transcoding method in order to guarantee QoS in streaming services by maximizing resource usage in a transcoding server equipped with both CPU and GPU computing units. The CPU and GPU computing units have different architectural features. The proposed method speculates workload of incoming transcoding requests and then schedules the requests either to the CPU or GPU accordingly. From performance evaluation, the proposed dual transcoding method achieved a speedup of 1.84 compared with traditional transcoding approach.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.3
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• pp.206-212
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• 2003

In this paper, we propose a mathematical optimization model with a suitable algorithm to determine delivery and backlogging quantities by minimizing the total cost including the penalty costs for delay. The system has fixed transshipment costs and demands are fulfilled by some delivery units that represent the volume of delivery amount to be shipped in a single time period. Since, backlogging is allowed, demands could be delivered later at the expense of some penalty costs. The model provides the optimal decisions on when and how much to he delivered while minimizing the total costs. To solve the problem, we propose an algorithm that uses the Lagrangian dual in conjunction with some primal heuristic techniques that exploit the special structure of the problem. Finally, we present some computational test results along with comments on the further study.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.246-248
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• 2009

In this paper, we will describe architecture and key characteristic for the DHS which is used in COMS. DHS is implemented in the fully redundant SCU, the dual redundant MIL-STD-1553B system bus, the payload interface units(MPIU and MI2U), the redundant ADE. the SCU interface with the other main digital units of the spacecraft through the MIL-STD-1553B.